參數(shù)資料
型號： MPC8377EWLANA
廠商： Freescale Semiconductor
文件頁數(shù)： 24/127頁
文件大?。?/td> 0K
描述： ACCESS POINT/ROUTER MPC8377
標準包裝： 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
12
Freescale Semiconductor
This table shows the estimated typical I/O power dissipation for the device.
600
400
1.45
2.1
3.4
4.1
300
1.45
2.0
3.3
4.0
667
333
1.45
2.1
3.3
4.1
266
1.45
2.0
3.3
3.9
800
400
1.45
2.5
3.8
4.3
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 6.
2. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MHz or VDD = 1.05 V for core frequencies of
800 MHz, and running a Dhrystone benchmark application.
3. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MHz or VDD = 1.05 V for core frequencies of
800 MHz, and running a Dhrystone benchmark application.
4. Maximum power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MHz or VDD = 1.05 V for core frequencies
of 800 MHz, worst case process, and running an artificial smoke test.
Table 6. Typical I/O Power Dissipation
Interface
Parameter
GVDD
(1.8 V)
GVDD/LBVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
L[1,2]_
nVDD
(1.0 V)
Unit
Comments
DDR I/O
65%
utilization
2 pair of
clocks
200 MHz data
rate, 32-bit
0.28
0.35
—
W
—
200 MHz data
rate, 64-bit
0.41
0.49
—
W
266 MHz data
rate, 32-bit
0.31
0.4
—
W
266 MHz data
rate, 64-bit
0.46
0.56
—
W
300 MHz data
rate, 32-bit
0.33
0.43
—
W
300 MHz data
rate, 64-bit
0.48
0.6
—
W
333 MHz data
rate, 32-bit
0.35
0.45
—
W
333 MHz data
rate, 64-bit
0.51
0.64
—
W
400 MHz
data rate,
32-bit
0.38
—
W
400 MHz
data rate,
64-bit
0.56
—
W
Table 5. Power Dissipation 1 (continued)
Core Frequency
(MHz)
CSB/DDR Frequency
(MHz)
Sleep Power
at Tj =65°C (W)
2
Typical Application
at Tj =65°C (W)
2
Typical Application
at Tj =125°C (W)
3
Max Application
at Tj =125°C (W)
4
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