參數(shù)資料
型號: MPC8377EWLANA
廠商: Freescale Semiconductor
文件頁數(shù): 17/127頁
文件大小: 0K
描述: ACCESS POINT/ROUTER MPC8377
標準包裝: 1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
113
23.3
Suggested PLL Configurations
This table shows suggested PLL configurations for different input clocks (LBCM = 0).
01
0001
11.5:1
4
10
0001
11.5:1
8
00
0010
02:1
2
01
0010
02:1
4
10
0010
02:1
8
00
0010
12.5:1
2
01
0010
12.5:1
4
10
0010
12.5:1
8
00
0011
03:1
2
01
0011
03:1
4
10
0011
03:1
8
00
0011
13.5:1
2
01
0011
13.5:1
4
10
0011
13.5:1
8
00
0100
04:1
2
01
0100
04:1
4
10
0100
04:1
8
Notes:
1. Core VCO frequency = Core frequency
× VCO divider. Note that VCO divider has to be set properly so that the core VCO
frequency is in the range of 800–1600 MHz.
Table 80. Example Clock Frequency Combinations
eLBC
e300 Core
Ref
LBCM DDRCM SVCOD SPMF
Sys
1,3 DDR data
rate
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
25.0
0
1
2
5
500
125
250
62.5
31.3
15.6
————
375
25.0
0
1
2
6
600
150
300
75 6
37.5
18.8
375
450
33.3
0
1
2
5
667
167
333
83.3 6
41.6
20.8
333
416
500
33.3
0
1
2
4
533
133
267
66.7
33.3
16.7
333
400
Table 79. e300 Core PLL Configuration (continued)
RCWLR[COREPLL]
core_clk : csb_clk Ratio
VCO Divider 1
0–1
2–5
6
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