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| 型號(hào)： | MPC8560VTAQFC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 23/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 783FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 36 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
21
DDR SDRAM
Figure 5 provides the AC test load for the DDR bus.
Figure 5. DDR AC Test Load
MDQS epilogue end
tDDSHME
1.5
4.0
ns
7, 8
Notes:
1.The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR
timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (OX or DX). For
example, tDDKHOV symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H)
state until outputs (O) are valid (V) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2.All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3.Maximum possible clock skew between a clock MCK[n] and its relative inverse clock MCK[n], or between a clock MCK[n]
and a relative clock MCK[m] or MSYNC_OUT. Skew measured between complementary signals at GVDD/2.
4.ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK and MDQ/MECC/MDM/MDQS.
5.Note that tDDSHMH follows the symbol conventions described in note 1. For example, tDDSHMH describes the DDR timing
(DD) from the rising edge of the MSYNC_IN clock (SH) until the MDQS signal is valid (MH). tDDSHMH can be modified
through control of the DQSS override bits in the TIMING_CFG_2 register. These controls allow the relationship between
the synchronous clock control timing and the source-synchronous DQS domain to be modified by the user. For best
turnaround times, these may need to be set to delay tDDSHMH an additional 0.25tMCK. This will also affect tDDSHMP and
tDDSHME accordingly. See the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual for
a description and understanding of the timing modifications enabled by use of these bits.
6.Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8560.
7.All outputs are referenced to the rising edge of MSYNC_IN (S) at the pins of the MPC8560. Note that tDDSHMP follows the
symbol conventions described in note 1. For example, tDDSHMP describes the DDR timing (DD) from the rising edge of
the MSYNC_IN clock (SH) for the duration of the MDQS signal precharge period (MP).
8.Guaranteed by design.
9.Guaranteed by characterization.
Table 17. DDR SDRAM Measurement Conditions
Symbol
DDR
Unit
Notes
VTH
MVREF ± 0.31 V
V
1
VOUT
0.5
× GVDD
V2
Notes:
1.Data input threshold measurement point.
2.Data output measurement point.
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued)
At recommended operating conditions with GVDD of 2.5 V ± 5%.
Parameter
Symbol 1
Min
Max
Unit
Notes
Output
GVDD/2
RL = 50 Ω
Z0 = 50 Ω
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