參數(shù)資料
型號: MPC8560VTAQFC
廠商: Freescale Semiconductor
文件頁數(shù): 28/108頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標準包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
26
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Figure 8 provides the AC test load for TSEC.
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
Figure 9. GMII Receive AC Timing Diagram
RX_CLK clock rise and fall time
tGRXR, tGRXF
2,3
——
1.0
ns
Note:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative
to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing
(GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of tGRX represents the GMII (G) receive
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Table 22. GMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V ± 5%, or LVDD=2.5V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Output
LVDD/2
RL = 50 Ω
Z0 = 50 Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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