參數(shù)資料
型號(hào): MPC8560VTAQFC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 68/108頁(yè)
文件大小: 0K
描述: MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
62
Freescale Semiconductor
RapidIO
Figure 43. Example Compliance Mask
Y = minimum data valid amplitude
Z = maximum amplitude
1 UI = 1 unit interval = 1/baud rate
X1 = end of zero crossing region
X2 = beginning of data valid window
DV = data valid window = 1 – 2
× X2
The waveform of the signal under test must fall within the unshaded area of the mask to be compliant.
Different masks are used for the driver output and the receiver input allowing each to be separately
specified.
13.3.1 RapidIO Driver AC Timing Specifications
Driver AC timing specifications are provided in Table 48, Table 49, and Table 50. A driver shall comply
with the specifications for each data rate/frequency for which operation of the driver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
The specifications apply for any combination of data patterns on the data signals.
The output of a driver shall be connected to a 100
Ω, ±1%, differential (bridged) resistive load.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7]).
Table 48. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential output high voltage
VOHD
200
540
mV
1
Differential output low voltage
VOLD
–540
–200
mV
1
X2
Z
0
Y
–Y
–Z
1–X2
DV
Di
ff
er
ent
ia
l(
V
)
Time (UI)
01
X1
1–X1
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