參數(shù)資料
型號: MPC8560VTAQFC
廠商: Freescale Semiconductor
文件頁數(shù): 88/108頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標準包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
80
Freescale Semiconductor
Clocking
15 Clocking
This section describes the PLL configuration of the MPC8560. Note that the platform clock is identical to
the CCB clock.
15.1 Clock Ranges
Table 55 provides the clocking specifications for the processor core and Table 56 provides the clocking
specifications for the memory bus.
Table 55. Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
667 MHz
833 MHz
1 GHz
Min
Max
Min
Max
Min
Max
e500 core processor frequency
400
667
400
833
400
1000
MHz
1, 2, 3
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage.
Table 56. Memory Bus Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
667 MHz
833 MHz
1 GHz
Min
Max
Min
Max
Min
Max
Memory bus frequency
100
166
100
166
100
166
MHz
1, 2, 3
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
settings.
2.The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage.
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