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參數(shù)資料
| 型號： | MPC8568EVTAUJJ |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 39/139頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
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MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
133
System Design Information
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
The following pins must NOT be pulled down during power-on reset: HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP, PA[5].
Three test pins also require pull-up resistors (100
Ω–1 KΩ). These pins are L1_TSTCLK, L2_TSTCLK,
and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal
machine operation.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
25.7
Configuration Pin Muxing
The MPC8568E provides the user with power-on configuration options which can be set through the use
of external pull-up or pull-down resistors of 4.7 k
Ω on certain output pins. These pins are generally used
as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip pull-up resistors of approximately 20 k
Ω. This value should permit the 4.7-kΩ resistor to
pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET
(and for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the
HRESET is negated, the pull-up resistor is also disabled, thus allowing functional operation of the pin as
an output with minimal signal quality or delay disruption. The default value for all configuration bits
treated this way has been encoded such that a high voltage level puts the device into the default state and
external resistors are needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
25.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement Power Architecture. The
device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not
interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, generally systems will assert TRST during power-on reset. Because the
JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying
TRST to HRESET is not practical.
The COP function of these processors allows a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
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