參數(shù)資料
型號(hào)： MPT612FBD48
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Maximum power point tracking IC
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48
文件頁(yè)數(shù)： 13/37頁(yè)
文件大?。?/td> 607K
代理商： MPT612FBD48
NXP Semiconductors
MPT612
Maximum power point tracking IC
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate
using one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer
The I
2
C-bus can also be used for test and diagnostic purposes
7.11 SPI serial I/O controller
The MPT612 contains one SPI I/O controller. SPI is a full duplex serial peripheral
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master and slave always send 8 bits to 16 bits of data
to each other. The controller provides the following features:
Compliant with SPI specification
Synchronous, Serial, Full Duplex, Communication
SPI Master only
Maximum data bit rate of one eighth of the input clock rate
7.12 SSP serial I/O controller
The MPT612 contains one SSP. The SSP controller is capable of operation on using
SPI, a 4-wire SSI or Microwire bus. It can interact with multiple masters and slaves on
the bus. However, only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with data frames of
4 bits to 16 bits flowing from the master to the slave and from the slave to the master.
Often only one of these data streams carries meaningful data. The controller provides the
following features:
Compatible with Motorola SPI, Texas Instruments 4-wire SSI and National
Semiconductor’s Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
Four bits to 16 bits per frame
7.13 General purpose 32-bit timers/external event counters
The Timer/Counter is designed to count cycles of:
the Peripheral CLocK (PCLK)
an externally supplied clock and optionally generate interrupts
perform other actions at specified timer values, based on four match registers.
It includes four capture inputs to trap the timer value when input signals transition which
can optionally generate an interrupt.
Multiple pins can be selected to perform a single capture or match function, for example
to provide an application with logical OR, AND and ‘broadcast’ functions.
MPT612
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 14 September 2010
13 of 13
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