
NXP Semiconductors
MPT612
Maximum power point tracking IC
7.15 Watchdog timer
The purpose of the watchdog timer is to reset the processor core after a given time if it
enters an error state. When enabled, the watchdog generates a system reset if the user
program fails to reload the watchdog within the predetermined time. The watchdog timer
provides the following features:
Internal device reset if not periodically reloaded
Debug mode
Enabled by software but requires a hardware reset or watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt, if enabled
Flag to indicate watchdog reset
Programmable 32-bit timer with internal prescaler
Selectable time period from (T
PCLK
× 256 × 4) to (T
PCLK
× 232 × 4) in multiples of
T
PCLK
× 4.
7.16 Real-time clock
The Real-Time Clock (RTC) is designed to provide a set of counters to measure time
when normal or idle operating mode is selected. The RTC has been designed to use
minimal power, making it suitable for battery powered systems where the CPU is not
running continuously (idle mode). The RTC provides the following features:
Measures the passage of time to maintain a calendar and clock
Ultra-low power design to support battery powered systems
Provides seconds, minutes, hours, day of the month, month, year, day of the week
and day of the year
Uses either the dedicated internal 32 kHz RTC oscillator input or the clock derived
from the external crystal/oscillator input on pin XTAL1
The programmable reference clock divider allows fine adjustment of the RTC
Dedicated power supply pin can be connected to a battery or the main 3.3 V supply
7.17 System control
7.17.1 Crystal oscillator
The on-chip integrated oscillator operates with external crystal in range of 1 MHz to
25 MHz. The oscillator output frequency is f
osc
and the ARM processor clock frequency is
CCLK. f
osc
and CCLK are the same value unless the PLL is running and connected.
7.17.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 70 MHz by a Current Controlled
Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. In practice however, the multiplier
value cannot be higher than 6 on this family of processor cores due to the CPUs upper
frequency limit.
The CCO operates in a range from 156 MHz to 320 MHz, this forms an additional divider
in the loop to keep the CCO within its frequency range while the PLL is providing the
required output frequency.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 September 2010
MPT612
NXP B.V. 2010. All rights reserved.
Product data sheet
15 of 15