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參數(shù)資料
| 型號： | MPT612FBD48 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Maximum power point tracking IC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT313-2, LQFP-48 |
| 文件頁數(shù)： | 17/37頁 |
| 文件大?。?/td> | 607K |
| 代理商： | MPT612FBD48 |
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NXP Semiconductors
MPT612
Maximum power point tracking IC
7.17.4 Code security (Code Read Protection)
The MPT612’s Code Read Protection (CRP) feature allows users to restrict access to the
on-board flash, JTAG and ISP using different levels of security. When needed, CRP is
activated by programming a specific pattern into a dedicated flash location. IAP
commands are not affected by the CRP.
Three levels of the CRP are implemented in boot loader code:
CRP1:
disables access to chip via the JTAG pins and allows partial flash updates
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors
cannot be erased
CRP2:
disables access to chip via the JTAG pins and only allows full flash erase and
update using a reduced set of the ISP commands
CRP3:
Running an application with this level fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using PIO14 pin.
It is up to the user’s application to provide a flash update mechanism (if needed)
using IAP calls or call the re-invoke ISP command to enable flash update via pin
UART0.
CAUTION
If Code Read Protection level three (CRP3) is selected, no future factory testing
can be performed on the device.
7.17.5 External interrupt inputs
The MPT612 includes up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. Optionally, the external interrupt inputs can be
used to wake-up the processor from Power-down mode and Deep power-down mode.
In additional, all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
7.17.6 Memory mapping control
The memory mapping control changes the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors can be mapped to the bottom of the on-chip
flash memory or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
7.17.7 Power control
The MPT612 supports three reduced power modes: Idle mode, Power-down mode and
Deep power-down mode.
In Idle mode, execution of instructions is suspended until a reset or interrupt is received.
Peripheral functions continue operation in Idle mode and can generate interrupts which
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clock
signals. The processor state and registers, peripheral registers and internal SRAM
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 14 September 2010
MPT612
NXP B.V. 2010. All rights reserved.
Product data sheet
17 of 17
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| MPT612FBD48,151 | 功能描述:ARM微控制器 - MCU 32b 32K Flash 28I/O RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據 RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| MPT612FBD48151 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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