參數(shù)資料
型號(hào)： MQ80C154-20P883
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44
封裝： CERAMIC, QFP-44
文件頁(yè)數(shù)： 10/101頁(yè)
文件大?。?/td> 3398K
代理商： MQ80C154-20P883
39
8168C-MCU Wireless-02/10
AT86RF212
No.
Symbol
Transition
Time, typ.
Comments
5
tTR5
PLL_ON
TRX_OFF
1 s
6
tTR6
TRX_OFF
RX_ON
200 s
Depends on external capacitor at AVDD (CB1 = 1 F nom.);
register bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is
not set; for details, refer to section 7.8.3
7
tTR7
RX_ON
TRX_OFF
1 s
8
tTR8
PLL_ON
RX_ON
1 s
9
tTR9
RX_ON
PLL_ON
1 s
Transition time is also valid for TX_ARET_ON / RX_AACK_ON
PLL_ON
10
tTR10
PLL_ON
BUSY_TX
1 symbol period When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START, first
symbol transmission is delayed by 1 symbol period (PLL settling
and PA ramp up)
11
tTR11
BUSY_TX
PLL_ON
32 s
PLL settling time, refer to section 7.8.3
12
tTR12
All states
TRX_OFF
1 s
Using TRX_CMD = FORCE_TRX_OFF (see register 0x02,
TRX_STATE); not valid for SLEEP
TRX_OFF (see tTR2)
13
tTR13
RESET
TRX_OFF
26 s
Not valid for reset in states P_ON or SLEEP
14
tTR14
Various
states
PLL_ON
1 s
Using TRX_CMD = FORCE_PLL_ON (see register 0x02,
TRX_STATE); not valid for states SLEEP, P_ON, RESET,
TRX_OFF, and *_NOCLK
The state transition timing is calculated based on the timing of the individual blocks
shown in Figure 5-3 to Figure 5-7. The worst case values include maximum operating
temperature, minimum supply voltage, and device parameter variations, see Table 5-2.
Table 5-2. Analog Block Initialization and Settling Times
Symbol Block
Time, typ.
Time, max.
Comments
tTR15
XOSC
330 s
1000 s
Leaving SLEEP state; depends on crystal oscillator setup (Siward
A207-011, CL = 10 pF)
tTR16
FTN
25 s
Filter tuning time
tTR17
DVREG
150 s
1500 s
Depends on external bypass capacitor at DVDD (CB3 = 1 F nom.,
10 F worst case), and on VDD
tTR18
AVREG
150 s
1500 s
Depends on external bypass capacitor at AVDD (CB1 = 1 F nom.,
10 F worst case) , and on VDD
tTR19
PLL, initial
200 s
370 s
PLL settling time TRX_OFF
PLL_ON, including 150 s AVREG
settling time (see tTR18)
tTR20
PLL, settling
11 s
42 s
Duration of a channel switch within frequency band, refer to section
tTR21
PLL, CF cal.
8 s
270 s
PLL center frequency calibration, refer to section 7.8.4
tTR22
PLL, DCU cal.
10 s
PLL DCU calibration, refer to section 7.8.4
tTR23
PLL, RX
TX
16 s
PLL settling time, refer to section 7.8.3
tTR24
PLL, TX
RX
32 s
PLL settling time, refer to section 7.8.3
tTR25
RSSI
BPSK-20: 32 s
BPSK-40: 24 s
O-QPSK: 8 s
RSSI update period in receive states, refer to section 6.4.2
tTR26
ED
8 symbol periods
ED measurement period; different timing with High Data Rate
Modes, see sections 6.5.2 and 7.1.4.3
tTR28
CCA
8 symbol periods
CCA measurement period, refer to section 6.6.2
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