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參數(shù)資料
| 型號(hào)： | MQ80C154-20P883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 66/101頁 |
| 文件大?。?/td> | 3398K |
| 代理商： | MQ80C154-20P883 |
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90
8168C-MCU Wireless-02/10
AT86RF212
Register 0x09 (CCA_THRES):
This register is relevant for the ED threshold when using LBT.
Table 6-37. Register 0x09 (CCA_THRES)
Bit
7
6
5
4
Name
Reserved
Read/Write
R/W
Reset Value
0
1
Bit
3
2
1
0
Name
CCA_ED_THRES
Read/Write
R/W
Reset Value
0
1
Bit 7:4 – Reserved
Bit 3:0 – CCA_ED_THRES
For CCA_MODE = 1, a busy channel is indicated if the measured received power is
above (RSSI_BASE_VAL + 2.07
CCA_ED_THRES) [dBm]. CCA_MODE = 0 and 3 are
logically related to this result.
Register 0x17 (XAH_CTRL_1):
This register is relevant for enabling or disabling the LBT mode.
Table 6-38. Register 0x17 (XAH_CTRL_1)
Bit
7
6
5
4
Name
Reserved
CSMA_LBT_MODE
AACK_FLTR_RES_FT
AACK_UPLD_RES_FT
Read/Write
R/W
Reset Value
0
Bit
3
2
1
0
Name
Reserved
AACK_ACK_TIME
AACK_PROM_MODE
Reserved
Read/Write
R
R/W
R
Reset Value
0
Bit 7 – Reserved
Bit 6 – CSMA_LBT_MODE
If set to 0 (default), CSMA-CA algorithm is used during TX_ARET for clear channel
assessment. Otherwise, the LBT specific listening mode is applied.
Bit 5:4 – AACK_FLTR_RES_FT, AACK_UPLD_RES_FT
Refer to section 5.2.6.
Bit 3 – Reserved
Bit 2:1 – AACK_ACK_TIME, AACK_PROM_MODE
Bit 0 – Reserved
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