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參數(shù)資料
| 型號： | MQ80C154-20P883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 53/101頁 |
| 文件大小： | 3398K |
| 代理商： | MQ80C154-20P883 |
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78
be the polynomial representing the sequence of bits for which the checksum is to be
computed. Multiply M(x) by
, giving the polynomial
16
x
16
)
(
)
(
x
M
x
N
=
.
Divide
modulo 2 by the generator polynomial
to obtain the remainder
polynomial
)
(x
N
)
(
16 x
G
15
14
1
15
0
...
)
(
r
x
r
x
r
x
r
x
R
+
=
The FCS field is given by the coefficients of the remainder polynomial
.
)
(x
R
Example:
Considering a 5-octet ACK frame, the MHR field consists of
0100 0000 0000 0000 0101 0110 .
The leftmost bit (b0) is transmitted first in time. The FCS would be
0010 0111 1001 1110 .
The leftmost bit (r0) is transmitted first in time.
6.3.3 Automatic FCS Generation
The automatic FCS generation is enabled with register bit TX_AUTO_CRC_ON = 1.
This allows the AT86RF212 to compute the FCS autonomously. For a frame with a
frame length field specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2
octets in the Frame Buffer and the resulting FCS octets are transmitted in place of the
last two octets of the Frame Buffer.
6.3.4 Automatic FCS Check
Basic and Extended Operating Modes are provided with an automatic FCS check for
received frames. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set to 1 if
the FCS of a received frame is valid. In addition, bit 7 of byte RX_STATUS is set
accordingly, refer to section 4.3.2.
In Extended Operating Mode, the RX_AACK procedure does not accept a frame if the
corresponding FCS is not valid, i.e. no TRX_END interrupt is issued. When operating in
TX_ARET mode, the FCS of a received ACK is automatically checked. If it is not
correct, the ACK is not accepted; refer to section 5.2.4 for automated retries.
6.3.5 Register Description
Register 0x04 (TRX_CTRL_1):
The TRX_CTRL_1 register is a multi-purpose register to control various operating
modes and settings of the radio transceiver, see Table 6-22.
Table 6-22. Register 0x04 (TRX_CTRL_1)
Bit
7
6
5
4
Name
PA_EXT_EN
IRQ_2_EXT_EN
TX_AUTO_CRC_ON
RX_BL_CTRL
Read/Write
R/W
Reset Value
0
1
0
Bit
3
2
1
0
Name
SPI_CMD_MODE
IRQ_MASK_MODE
IRQ_POLARITY
Read/Write
R/W
Reset Value
0
AT86RF212
8168C-MCU Wireless-02/10
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