參數(shù)資料
型號: MS81V06160
廠商: OKI SEMICONDUCTOR CO., LTD.
元件分類: DRAM
英文描述: (401,408-word ⅴ 16-bit) FIFO memory
中文描述: (401408字ⅴ16位),F(xiàn)IFO存儲器
文件頁數(shù): 8/18頁
文件大?。?/td> 266K
代理商: MS81V06160
Semiconductor
MS81V06160
8/18
AC Characteristics
(V
CC
= 3.3 V ± 10%, Ta = 0 to 70°C)
MS81V06160-15
Min.
Max.
3
3
6
6
3
1.5
3
1.5
3
1.5
3
1.5
3
1.5
6
6
6
6
3
1.5
6
6
3
1.5
3
1.5
3
1.5
3
1.5
6
6
6
6
3
1.5
15
15
1
3
3
1,600
1,600
MS81V06160-12
Min.
3
3
4
4
3
1
3
1
3
1
3
1
3
1
4
4
4
4
3
1
4
4
3
1
3
1
3
1
3
1
4
4
4
4
3
1
12
12
1
3
3
1,600
1,600
Parameter
Symbol
Max.
9
9
5
Unit
Access Time from SRCK
D
OUT
Hold Time from SRCK
D
OUT
Enable Time from SRCK
SWCK “H” Pulse Width
SWCK “L” Pulse Width
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
WE “H” Pulse Width
WE “L” Pulse Width
IE “H” Pulse Width
IE “L” Pulse Width
RSTW Setup Time
RSTW Hold Time
SRCK “H” Pulse Width
SRCK “L” Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable Setup Time
RE Disable Hold Time
OE Enable Setup Time
OE Enable Hold Time
OE Disable Setup Time
OE Disable Hold Time
RE “H” Pulse Width
RE “L” Pulse Width
OE “H” Pulse Width
OE “L” Pulse Width
RSTR Setup Time
RSTR Hold Time
SWCK Cycle Time
SRCK Cycle Time
Transition Time (Rise and Fall)
WE “L” Period before W Reset
RE “L” Period before R Reset
RE Delay after Reset
WE Delay after Reset
t
AC
t
DDCK
t
DECK
t
WSWH
t
WSWL
t
DS
t
DH
t
WENS
t
WENH
t
WDSS
t
WDSH
t
IENS
t
IENH
t
IDSS
t
IDSH
t
WWEH
t
WWEL
t
WIEH
t
WIEL
t
RSTWS
t
RSTWH
t
WSRH
t
WSRL
t
RENS
t
RENH
t
RDSS
t
RDSH
t
OENS
t
OENH
t
ODSS
t
ODSH
t
WREH
t
WREL
t
WOEH
t
WOEL
t
RSTRS
t
RSTRH
t
SWC
t
SRC
t
T
t
LWE
t
LRE
t
FRD
t
FWD
12
12
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk
clk
ns
ns
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