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參數(shù)資料
| 型號： | MS81V06160 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 元件分類： | DRAM |
| 英文描述： | (401,408-word ⅴ 16-bit) FIFO memory |
| 中文描述： | （401408字ⅴ16位），F(xiàn)IFO存儲器 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 266K |
| 代理商： | MS81V06160 |
Semiconductor
MS81V06160
6/18
Serial Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Serial Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MS8106160.
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