- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45388 > MSC8156SVT1000B (FREESCALE SEMICONDUCTOR INC) 0-BIT, OTHER DSP, PBGA783 PDF資料下載
參數(shù)資料
| 型號： | MSC8156SVT1000B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8156SVT1000B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
30
2.5.2.3
SerDes Transmitter and Receiver Reference Circuits
Figure 6 shows the reference circuits for SerDes data lane transmitter and receiver.
2.5.3
DC-Level Requirements for SerDes Interfaces
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.5.3.1
DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 7 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
Figure 6. SerDes Transmitter and Receiver Reference Circuits
Figure 7. Differential Reference Clock Input DC Requirements (External DC-Coupled)
50
Ω
50
Ω
50
Ω
50
Ω
Transmitter
Receiver
SR[1–2]_TXm
SR[1–2]_RXm
SR[1–2]_TXm
SR[1–2]_RXm
Note: The [1–2] indicates the specific SerDes Interface (1 or 2) and the m indicates the
specific channel within that interface (0,1,2,3). Actual signals are assigned by the
HRCW assignments at reset (see Chapter 5, Reset in the reference manual for details)
SR[1–2]_REF_CLK
Vmax < 800 mV
Vmin > 0V
100 mV < Vcm < 400 mV
200 mV < Input Amplitude or Differential Peak < 800 mV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8254TVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254SVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254TVT1000B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8256SVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8256TVT800B | 0-BIT, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8156SVT1200B | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
| MSC8156TAG1000B | 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 6X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 6X 1GHZ SC3850 783FCBGA |
| MSC8156TVT1000A | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
| MSC8156TVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP StarCore 6-cores RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC8156TVT1200B | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。