- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45388 > MSC8156SVT1000B (FREESCALE SEMICONDUCTOR INC) 0-BIT, OTHER DSP, PBGA783 PDF資料下載
參數(shù)資料
| 型號： | MSC8156SVT1000B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8156SVT1000B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Electrical Characteristics
MSC8156 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
31
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 8 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
Single-Ended Mode
— The reference clock can also be single-ended. The SR[1–2]_REF_CLK input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SR[1–2]_REF_CLK either left
unconnected or tied to ground.
— The SR[1–2]_REF_CLK input average voltage must be between 200 and 400 mV. Figure 9 shows the SerDes
reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SR[1–2]_REF_CLK) through the same source impedance as the clock input (SR[1–2]_REF_CLK) in use.
2.5.3.2
DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The
MSC8156 supports a 2.5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 1.0a. The
transmitter specifications are defined in Table 11 and the receiver specifications are defined in Table 12.
Figure 8. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 9. Single-Ended Reference Clock Input DC Requirements
SR[1–2]_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SR[1–2]_REF_CLK
400 mV < SR[1–2]_REF_CLK Input Amplitude < 800 mV
0V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSC8254TVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254SVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8254TVT1000B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8256SVT800B | 0-BIT, OTHER DSP, PBGA783 |
| MSC8256TVT800B | 0-BIT, OTHER DSP, PBGA783 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSC8156SVT1200B | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
| MSC8156TAG1000B | 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 6X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 6X 1GHZ SC3850 783FCBGA |
| MSC8156TVT1000A | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
| MSC8156TVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP StarCore 6-cores RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC8156TVT1200B | 制造商:Freescale Semiconductor 功能描述:DSP, STARCORE, 6-CORES - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。