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參數(shù)資料
| 型號： | MSM5424331 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 222,720-Word 】 24-Bit Field Memory |
| 中文描述： | 222720詞】24位場記憶 |
| 文件頁數(shù)： | 11/34頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MSM5424331 |
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FEDS5424331-01
1
Semiconductor
MSM5424331
11/34
2.
2.1 Read operation
Before the read operation begins, the X address (or line address) must be input for setting initial bit address
for the following serial read access.
When
RE
is low, a set of serial 24-bit-width read data on DO0-11, DO12-23 pins is read from read registers
attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
Read
2.2 Read address pointer increment operation
The read address pointer is incremented synchronized with RCLK when
RE
level is low.
The output data will be undefined when the read address pointer is incremented above the last address of one
line.
3.
Initial Address Setting (Write/Read Independent)
Any read operations are prohibited in the read initial address set period. Similarly, any write operations are
prohibited in the write initial address set period. Note that read initial address set and write initial address set
can occur independently. Similarly, read access can be achieved independently from write initial address set
period and write access can be achieved independently from read initial address set cycles.
3.1 Write address setting
WADE/RX enables initial read address inputs. When WADE/RX is high, 10 bits of serial X address (or line
address) are input from higher order bits from WXAD.
The operations above enable selection of specific lines randomly and enables the start of serial write access
synchronized with write clock WCLK. Address for each line must be input between each line access. In other
words, MSM5424331’s write is achieved in a “l(fā)ine by line” manner. Any write operations are prohibited in
the initial write address set periods.
Serial write input enable time t
must be kept for starting a serial write just after the initial write address set
period. The most significant bit (A9) is ignored.
3.2 Read address setting
RADE/RX enables initial read address inputs.
When RADE/RX is high, 10 bits of serial X address (or line address) are input from higher order bits from
RXAD.
The operations above enable selection of specific lines randomly and enables the start of serial read access
synchronized with read clocks, RCLK. Address for each line must be input between each line access. In other
words, MSM5424331’s read operation is achieved in “l(fā)ine by line” manner.
Any read operations are prohibited in the initial read address set periods. Serial read operations are prohibited
while RADE/RX is high. Serial read port enable time t
SRE
must be kept for starting a serial read just after the
initial read address set period. The most significant bit (A9) is ignored.
相關(guān)PDF資料 |
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|---|---|
| MSM5424331TS-AK | 222,720-Word 】 24-Bit Field Memory |
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