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參數(shù)資料
| 型號： | MSM5424331 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 222,720-Word 】 24-Bit Field Memory |
| 中文描述： | 222720詞】24位場記憶 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MSM5424331 |
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FEDS5424331-01
1
Semiconductor
MSM5424331
8/34
Write Related
WCLK: Write Clock
WCLK is a write control clock input in the FIFO mode. Synchronized with WCLK’s rising edge, serial write
access into write ports is executed when
LWE
or
UWE
is low.
According to WCLK clocks, the internal counter for the serial address is incremented automatically.
In a write address set cycle, all the write addresses which were input from WXAD are stored into internal address
registers synchronously with WCLK. In this address set cycle, WADE/RX must be held high and WR/TR must be
held low.
In the write address reset cycle, various write address reset modes can be set synchronously with WCLK. These
reset cycles replace complicated serial address control with simple reset cycle control which requires only one
WCLK cycle. It greatly facilitates memory access.
In the Block Access mode, the WCLK signal is ignored.
LWE
: Write Enable
LWE
is a write enable clock input in the FIFO mode.
LWE
enables or disables both internal write address pointers
and data-in buffers. When
LWE
is low, the internal write address pointer is incremented synchronously with
WCLK. When
LWE
is high, even if WCLK is input, the internal write address pointer is not incremented.
In the Block Access mode, writing in the L-bank is performed when
LWE
goes low at the falling edge of DIN0
(RAS
).
UWE
: Write Enable
UWE
is a write enable clock input in the FIFO mode.
UWE
enables or disables both internal write address
pointers and data-in buffers. When
UWE
is low, the internal write address pointer is incremented synchronously
with WCLK. When
UWE
is high, even if WCLK is input, the internal write address pointer is not incremented.
In the Block Access mode, writing in the U-bank is performed when
UWE
goes low at the falling edge of DIN0
(
RAS
).
DIN0 (
RAS
): Data-In
DIN0 is serial data-in in the FIFO mode.
In the Block Access mode, this pin serves as
RAS
. On the falling edge of this signal, the 10-bit row address (A0 to
A9) is fetched.
DIN1 (
CAS
): Data-In
DIN1 is serial data-in in the FIFO mode.
In the Block Access mode, this pin serves as
CAS
. On the falling edge of this signal, the 10-bit column address
(A0 to A9) is fetched. This column address becomes a start address in the Block Access mode. When DIN1
(
CAS
) is toggled while DIN0 (
RAS
) remains low, the read/write operation in the Block Access mode is enabled.
DIN2-11 (A0-A9): Data-Ins
DIN2-11 are serial data-ins in the FIFO mode.
In the Block Access mode, these pins serve as a row or column address input (A0 to A9). These pins fetch a row
address when DIN0 (
RAS
) is active or a column address when DIN1 (
CAS)
is active.
DIN12-23: Data-Ins
DIN12-23 are serial data-ins in the FIFO mode.
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PDF描述 |
|---|---|
| MSM5424331TS-AK | 222,720-Word 】 24-Bit Field Memory |
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| MSM5432126A-40GS-K | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5432126A-45 | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
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