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參數(shù)資料
| 型號： | MSM5424331 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 222,720-Word 】 24-Bit Field Memory |
| 中文描述： | 222720詞】24位場記憶 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MSM5424331 |
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FEDS5424331-01
1
Semiconductor
MSM5424331
13/34
Block Access Mode
The Block Access mode is configured when the D/F pin is set high.
1.
Write Operation
The MSM5424331 fetches a 10-bit row address form lines A0 to A9 at the falling edge of the DIN0 (
RAS
)
pin and a 10-bit column address (10 bits long) from the lines at the falling edge of the DIN1 (
CAS
) pin. With
this operation, a head address can be set arbitrarily.
For a write operation, the
LWE
or
UWE
pin must be set low at the falling edge of DIN0 (
RAS
). The actual
fetching of write data is performed at the falling edge of DIN1 (
CAS
) after t
CASB
. The write data is entered
from I/O pins DQ0 to DQ11. The write data is written in the L-bank at the falling edge of DIN0 (
RAS
) when
LWE
is low and
UWE
is high or in the U-bank when
LWE
is high and
UWE
is low. When both
LWE
and
UWE
are both low, data is written in either the L- or U-bank (which is undefined).
Data storage in the memory cell is executed at the rising edge of DIN0 (
RAS
) after the block write operation
is completed.
When changing a write operation in the FIFO mode to a write operation in the Block Access mode, it is
required to monitor on the WAIT pin whether self refresh in the FIFO mode is completed. Perform the block
write operation after the output of the WAIT pin is high.
The block read operation and FIFO operation are disabled during a block write operation.
2.
Read Operation
The MSM5424331 fetches a 10-bit row address from lines A0 to A9 at the falling edge of the DIN0 (
RAS
)
pin and a 10-bit column address from the lines at the falling edge of the DIN1 (
CAS
) pin. With this operation,
a head address can be set randomly.
For a read operation, the
LWE
or
UWE
pin must be set high at the falling edge of DIN0 (
RAS
). Read data is
fetches at the falling edge of DIN1 (
CAS
) after t
CASB
. The
RE
pin should be set low at the falling edge of
DIN1 (
CAS
).
The read data is output from DQ0 to DQ11 I/O pins. The L- or U-bank from which data is read is selected by
the status of the “A9” bit of the row address. Data is read from the L-bank when the “A9” bit is “0” or from
the U-bank when the “A9” bit is “1”. When changing a read operation in the FIFO mode to a read operation
in the Block Access mode, it is required to monitor on the WAIT pin whether self refresh in the FIFO mode is
completed. Perform the block read operation after the output of the WAIT pin is high.
The block write operation and FIFO operation are disabled during a block read operation.
Refresh
1.
FIFO Mode
In the FIFO mode, the MSM5424331 performs self refresh.
2.
Block Access Mode
In the Block Access mode, self refresh is disabled. Use the
CAS
before
RAS
refresh function to refresh.
Addressing from A0 to A9 pins is not required because refresh addresses are automatically given by the
built-in refresh counter.
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PDF描述 |
|---|---|
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