- 您現在的位置：買賣IC網 > PDF目錄378013 > MSM5424331 (OKI SEMICONDUCTOR CO., LTD.) 222,720-Word 】 24-Bit Field Memory PDF資料下載
參數資料
| 型號： | MSM5424331 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 222,720-Word 】 24-Bit Field Memory |
| 中文描述： | 222720詞】24位場記憶 |
| 文件頁數： | 12/34頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MSM5424331 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
FEDS5424331-01
1
Semiconductor
MSM5424331
12/34
4.
Initial Address Reset Modes (Write/Read Independent)
The initial address reset modes replace complicated read or write initial address settings with simple reset
cycles. Initial address reset modes are selected by RR high during read and WR/TR high during write. As in
normal read or write address settings, any read operations are prohibited in the read address reset cycles.
Similarly, any write operations are prohibited in the initial write address reset cycles. Note that read initial
address reset and write initial address reset can occur independently.
Similarly, read access can be achieved independently from write initial address reset cycles and write access
can be achieved independently from read initial address reset cycles.
Input addresses are stored into address registers which are connected with address counter which controls
address pointer operation. In the serial access operation, the input address into the address registers are kept.
Serial write data input enable time t
SWE
and serial read port read enable time t
SRE
must be kept for starting
serial read or write just after the initial read or write address reset cycles.
Refer to the “FUNCTION TABLE” shown later.
4.1 Line hold operation (read only)
By the “Line hold operation” logic which is composed by a combination of control inputs’ level, access is
executed starting from the first word on the current line.
4.2 Original address reset operation
By the “Original address reset” logic, the address counter is set to (0,0). After the reset mode, serial access
starts from the address (0,0) .
The address counter is reset by this reset mode but the address register, which stored input address in the
previous address reset cycle or address set cycle, is not reset. The non-initialized address can be used as a
preset address in “address jump reset” mode.
4.3 Line increment operation
By the “Line increment operation” logic, the X address counter is incremented by one from the current X
address. That is, serial access from the Y = (0) on the next line is enabled.
4.4 Address jump operation
By the “Address jump operation” logic, a jump may be caused to the initialized line address.
Note: During one reset setting cycle, a plurality of resets cannot be set.
相關PDF資料 |
PDF描述 |
|---|---|
| MSM5424331TS-AK | 222,720-Word 】 24-Bit Field Memory |
| MSM5432126A | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5432126A-40 | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5432126A-40GS-K | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5432126A-45 | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MSM548262-60JS | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-60T3-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-60TK | 制造商:OK International 功能描述: |
| MSM548262-60TS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-70JS | 制造商:ROHM Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。