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| 型號(hào)： | MSM9225BGA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 27/95頁(yè) |
| 文件大?。?/td> | 567K |
| 代理商： | MSM9225BGA-2K |
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MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 20
2.4.2 CAN Interrupt Control Register (CANI: 0Fhex)
This register controls CAN interrupts.
The bit configuration is as follows:
MSB
MEINT
IEF
IRF
ITF
Not
used
EINTE EINTR EINTT
LSB
CANI (0Fhex), *R/W: R/W
Initial
value:
00
0
Transmission complete interrupt output
disable
1
Transmission complete interrupt output
enable
0
Receive complete interrupt output
disable
1
Receive complete interrupt output
enable
0
Error interrupt output disable
1
Error interrupt output enable
Unused bit.
Write a “0”.
0
Clear transmission complete interrupt
request flag
1
Transmission complete interrupt
generated
0
Clear receive complete interrupt request
flag
1
Receive complete interrupt generated
0
Clear error interrupt request flag
1
Error interrupt generated
0
Output to the interrupt output pin is
disabled
1
Output to the interrupt output pin is
enabled
* ITF, IRF, and IEF are in the read-only state when they are “1”. “1” cannot be written.
Figure 2-19 CAN Interrupt Control Register (CANI)
(1) Transmission complete interrupt output enable: EINTT
This bit is used to output transmission complete interrupt signal INTT from interrupt pin
INT when
transmission completes.
When EINTT is “0”, a transmission complete interrupt signal is not output from the interrupt pin.
When EINTT is “1”, a transmission complete interrupt signal is output from the interrupt pin.
At reset, EINTT is set to “0”.
(2) Receive complete interrupt output enable: EINTR
This bit is used to output receive complete interrupt signal INTR from interrupt pin
INT when reception
completes.
When EINTR is “0”, a receive complete interrupt signal is not output from the interrupt pin.
When EINTR is “1”, a receive complete interrupt signal is output from the interrupt pin.
At reset, EINTR is set to “0”.
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