參數(shù)資料
型號： MSM9225BGA-2K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： PLASTIC, QFP-44
文件頁數(shù)： 28/95頁
文件大?。?/td> 567K
代理商： MSM9225BGA-2K
MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 21
(3) Error interrupt output enable: EINTE
When an error occurs, this bit is used to output error interrupt signal INTE from interrupt pin
INT.
When EINTE is “0”, an error interrupt signal is not output from the interrupt pin.
When EINTE is “1”, an error interrupt signal is output from the interrupt pin.
At reset, EINTE is set to “0”.
(4) Transmission complete interrupt request flag: ITF
ITF becomes “1” when a transmission complete interrupt is generated. Only “0” can be written to this bit.
At reset, ITF is set to “0”.
(5) Receive complete interrupt request flag: IRF
IRF becomes “1” when a receive complete interrupt is generated. Only “0” can be written to this bit.
At reset, IRF is set to “0”.
(6) Error interrupt request flag: IEF
IEF becomes “1” when an error occurs. Only “0” can be written to this bit.
At reset, IEF is set to “0”.
(7) Master interrupt control enable: MEINT
This bit is used to set enable/disable of interrupts.
The outline of interrupt control is shown in Figure 2-20.
When MEINT is “0”, interrupt request control is disabled.
When MEINT is “1”, interrupt request control is enabled.
At reset, MEINT is set to “0”.
EIT (for each message box)
ITF
INTT
INTR
Interrupt cause (transmission completed)
EINTT
1
0
IRF
Interrupt cause (reception completed)
EINTR
1
0
EINTE
1
0
IEF
Interrupt cause (an error occurred)
MEINT
1
0
INTpin
EIR (for each message box)
INTE
Figure 2-20 Interrupt Control
* INT signal generator circuit
This signal changes to “L”
from “H” when an interrpt
request is generated, and is
automatically set to “H” again
after 32 Ts (T-1/fosc).
INTpin
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