參數(shù)資料
型號： MSP430BT5190IZQW
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PBGA113
封裝： LEAD FREE, PLASTIC, BGA-113
文件頁數(shù)： 58/97頁
文件大?。?/td> 724K
代理商： MSP430BT5190IZQW
PRODUCTPREVIEW
MSP430BT5190
www.ti.com
SLAS703 – APRIL 2010
12-Bit ADC, Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
AVCC and DVCC are connected together,
Analog supply voltage
AVCC
AVSS and DVSS are connected together,
2.2
3.6
V
Full performance
V(AVSS) = V(DVSS) = 0 V
V(Ax)
Analog input voltage range(2)
All ADC12 analog input pins Ax
0
AVCC
V
fADC12CLK = 5.0 MHz, ADC12ON = 1,
2.2 V
125
155
Operating supply current into
IADC12_A
REFON = 0, SHT0 = 0, SHT1 = 0,
A
AVCC terminal
(3)
3 V
150
220
ADC12DIV = 0
Only one terminal Ax can be selected at one
CI
Input capacitance
2.2 V
20
25
pF
time
RI
Input MUX ON resistance
0 V
≤ VAx ≤ AVCC
10
200
1900
(1)
The leakage current is specified by the digital I/O input leakage.
(2)
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. If the
reference voltage is supplied by an external source or if the internal reference voltage is used and REFOUT = 1, then decoupling
capacitors are required. See REF, External Reference andREF, Built-In Reference.
(3)
The internal reference supply current is not included in current consumption parameter IADC12_A.
12-Bit ADC, Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC12 linearity
fADC12CLK
2.2 V/3 V
0.45
4.8
5.4
MHz
parameters
Internal ADC12
fADC12OSC
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V/3 V
4.2
4.8
5.4
MHz
oscillator(1)
REFON = 0, Internal oscillator,
2.2 V/3 V
2.4
3.1
fADC12OSC = 4.2 MHz to 5.4 MHz
tCONVERT
Conversion time
s
External fADC12CLK from ACLK, MCLK or SMCLK,
(2)
ADC12SSEL
≠ 0
RS = 400 , RI = 1000 , CI = 20 pF,
tSample
Sampling time
2.2 V/3 V
1000
ns
t = [RS + RI] × CI
(3)
(1)
The ADC12OSC is sourced directly from MODOSC inside the UCS.
(2)
13 × ADC12DIV × 1/fADC12CLK
(3)
Approximately ten Tau (t) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2
n+1) x (R
S + RI) × CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance
12-Bit ADC, Linearity Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
1.4 V
≤ (VeREF+ – VREF–/VeREF–)min ≤ 1.6 V
±2
Integral
EI
2.2 V/3 V
LSB
linearity error (INL)
1.6 V < (VeREF+ – VREF–/VeREF–)min ≤ VAVCC
±1.7
Differential
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
ED
2.2 V/3 V
±1.0
LSB
linearity error (DNL)
CVREF+ = 20 pF
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
EO
Offset error
2.2 V/3 V
±1.0
±2.0
LSB
Internal impedance of source RS < 100 , CVREF+ = 20 pF
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
EG
Gain error
2.2 V/3 V
±1.0
±2.0
LSB
CVREF+ = 20 pF
Total unadjusted
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
ET
2.2 V/3 V
±1.4
±3.5
LSB
error
CVREF+ = 20 pF
Copyright 2010, Texas Instruments Incorporated
61
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