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參數(shù)資料
| 型號： | MSP430C336IPJM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 3.8 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, MS-022, QFP-100 |
| 文件頁數(shù)： | 14/42頁 |
| 文件大?。?/td> | 637K |
| 代理商： | MSP430C336IPJM |
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MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
inputs and outputs
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
t(int)
External interrupt timing
Port P0, P1 to P2:
External trigger signal for the interrupt
flag (see Notes 13 and 14)
3 V/5 V
1.5
cycle
t(cap)
Timer_A, capture timing
TA0-TA4
External capture signal (see Note 15)
3 V/5 V
250
ns
f(IN)
P0 1 CIN TP 0 5 UCLK SIMO SOMI
3 V/5 V
DC
f(system)
MHz
t(H) or t(L)
Input frequency
P0.1, CIN, TP 0.5, UCLK, SIMO, SOMI,
TACLK TA0-TA4
3 V
300
f(system)
ns
t(H) or t(L)
TACLK, TA0-TA4
5 V
300
f(system)
ns
f(XBUF)
XBUF, CL = 20 pF
3 V/5 V
f(system)
f(TAx)
Output frequency
TA0-4, CL = 20 pF
3 V/5 V
DC
f(system)/2
MHz
f(UCLK)
UCLK, CL = 20 pF
3 V/5 V
DC
f(system)
t(Xdc)
XBUF, CL = 20 pF
f(MCLK)= 1.1 MHz
f(XBUF) = f(ACLK)
f(XBUF) = f(ACLK/n)
3 V/5 V
40%
35%
50
60%
65%
t(TA)
Duty cycle of output
TA0..4, CL = 20 pF
t(TAH)= t(TAL)
3 V/5 V
0
±100
ns
t(UC)
UCLK, C(L) = 15pF
t(UCH)= t(UCL)
3 V/5 V
0
±100
ns
t(
τ)
USART: Deglitch time
See Note16
3 V
5 V
0.6
0.3
2.6
1.4
s
NOTES: 13. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int). The
conditions to set the flag must be met independently from this timing constraint. T(int) is defined in MCLK cycles.
14. The external interrupt signal cannot exceed the maximum input frequency (f(in))
15. The external capture signal triggers the capture event every time t(cap) is met. It may be triggered even with capture signals shorter
than t(cap). The conditions to set the flag must be met independently from this timing constraint.
16. The signal applied to the USART receive signal/terminal (URXD) should meet the timing requirements of t(
τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(
τ). The operating conditions
to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on
the URXD line.
LCD
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
V(33)
Voltage at R33
2.5
VCC+0.2
V(23)
Analog voltage
Voltage at R23
VCC = 3 V/5 V
(V33–V03) × 2/3 + V03
V
V(13)
Analog voltage
Voltage at R13
VCC = 3 V/5 V
(V(33)–V(03)) × 1/3 + V(03)
V
V(03)
Voltage at R03
V(33) – 2.5
VCC+0.2
VO(HLCD) Output 1
I(HLCD)<= 10 nA
VCC = 3 V/5 V
V(R33) – 0.125
VCC
V
VO(LLCD)
Output 0
I(LLCD) <= 10 nA
VCC = 3 V/5 V
VSS
VSS + 0.125
V
I(R03)
R03 = VSS
No load at all
td
±20
I(R13)
Input leakage
R13 = VCC/3
segment and
common lines,
±20
nA
I(R23)
R23 = 2
× VCC/3
common lines,
VCC = 3 V/5 V
±20
V(Sxx0)
V(03)
V(03) – 0.1
V(Sxx1)
Segment line
I(S )=3 A
VCC = 3 V/5 V
V(13)
V(13) – 0.1
V
V(Sxx2)
g
voltage
I(Sxx)= – 3 A,
VCC = 3 V/5 V
V(23)
V(23) – 0.1
V
V(Sxx3)
V(33)
V(33) + 0.1
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| MSP430C336PJM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLERS |
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| MSP430C337HFD | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLERS |
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| MSP430C337PJM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MIXED SIGNAL MICROCONTROLLERS |
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