MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
TMS
94
I
Test mode select. TMS is used as an input port for device programming and test.
TDO/TDI
92
I/O
Test data output port. TDO/TDI data output or programming data input terminal
TP0.0
3
O
General-purpose 3-state digital output port, bit 0 – Timer/Port
TP0.1
4
O
General-purpose 3-state digital output port, bit 1 – Timer/Port
TP0.2
5
O
General-purpose 3-state digital output port, bit 2 – Timer/Port
TP0.3
6
O
General-purpose 3-state digital output port, bit 3 – Timer/Port
TP0.4
7
O
General-purpose 3-state digital output port, bit 4 – Timer/Port
TP0.5
8
I/O
General-purpose 3-state digital input/output port, bit 5 – Timer/Port
VCC1
1
Positive supply voltage
VCC2
29
Positive supply voltage
VSS1
100
Ground reference
VSS2
28
Ground reference
VSS3
52
Ground reference
XBUF
97
O
System clock (MCLK) or crystal clock (ACLK) output
Xin
99
I
Input port for crystal oscillator
Xout/TCLK
98
I/O
Output terminal of crystal oscillator or test clock input
detailed description
processing unit
The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, which is
distinguished by ease of programming. All operations other than program-flow instructions consequently are
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.
CPU registers
The CPU has sixteen registers that provide
reduced instruction execution time. This reduces
the register-to-register operation execution time
to one cycle of the processor frequency.
Four of the registers are reserved for special use
as a program counter, a stack pointer, a status
register, and a constant generator. The remaining
registers are available as general-purpose regis-
ters.
Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory manipula-
tion.
Program Counter
General-Purpose Register
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
R5
General-Purpose Register
R14
General-Purpose Register
R15