MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS
SLAS227A – OCTOBER 1999 – REVISED JUNE 2000
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operation modes and interrupts
The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow-energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK, a multiple of ACLK, is used as the system clock.
The following five operating modes are supported:
D Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
D Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
D Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
D Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
D Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(
MCLK generator) is switched off.
D Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled, however, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
The most general bits that influence current consumption and support fast turnon from low power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.
Reserved For Future
Enhancements
15
9
8
7
0
V
SCG1
SCG0
OscOff
CPUOff
GIE
N
Z
C
rw-0
interrupts
Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits,
the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming
of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address
locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler
instruction sequence. Table 3 provides a summation of interrupt functions and addresses.