參數(shù)資料
型號(hào)： MT46V128M4P-75L:C
元件分類： DRAM
英文描述： 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝： 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁(yè)數(shù)： 16/94頁(yè)
文件大小： 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
23
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Commands
one or all banks are to be precharged, and in the case where only one bank is to be pre-
charged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank. A PRECHARGE com-
mand will be treated as a NOP if there is no open row in that bank (idle state), or if the
previously open row is already in the process of precharging.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge func-
tion described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the READ or WRITE burst. Auto
precharge is either enabled or disabled for each individual READ or WRITE command.
This device supports concurrent auto precharge if the command to the other bank does
not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 25. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with auto precharge
disabled). The most recently registered READ command prior to the BURST TERMI-
NATE command will be truncated, as shown in “Operations” on page 25. The open page
from which the READ burst was terminated remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous
to CAS#-BEFORE-RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonper-
sistent, so it must be issued each time a refresh is required. All banks must be idle before
an AUTO REFRESH command is issued.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 512Mb DDR SDRAM
requires AUTO REFRESH cycles at an average interval of 7.8125s (MAX).
To allow for improved efficiency in scheduling and switching between tasks, some flexi-
bility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, meaning that the maximum abso-
lute interval between any AUTO REFRESH command and the next AUTO REFRESH
command is 9 x 7.8125s (70.3s). JEDEC specifications only allows 8 x 7.8125s; Micron
specification exceeds the JEDEC requirement by one clock. This maximum absolute
interval is to allow future support for DLL updates internal to the DDR SDRAM to be
restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between
updates.
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends tRFC later.
相關(guān)PDF資料
PDF描述
MT46V128M4P-75ZLIT:C 128M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4TG-75E 64M X 4 DDR DRAM, 0.75 ns, PDSO66
MT46V64M4FG-75Z 64M X 4 DDR DRAM, 0.75 ns, PBGA60
MT47H128M8HQ-3AT 128M X 8 DDR DRAM, 0.4 ns, PBGA60
MT47H64M16HR-3IT 64M X 16 DDR DRAM, 0.4 ns, PBGA84
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V128M4T67A3WC1 制造商:Micron Technology Inc 功能描述:128MX4 DDR SDRAM DIE-COM COMMERCIAL 2.5V - Trays
MT46V128M4TG-5B/D 制造商:Samsung Semiconductor 功能描述:
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