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DDR2 SDRAM
MT47R256M4 – 32 Meg x 4 x 8 banks
MT47R128M8 – 16 Meg x 8 x 8 banks
MT47R64M16 – 8 Meg x 16 x 8 banks
Features
VDD/VDDQ = +1.55V, 1.5–1.9V range
Backward compatible with 1.8V DDR2
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Selectable burst lengths (BL): 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS compliant
Supports JEDEC clock jitter specification
Very low power operation
Marking
Configuration
– 256 Meg x 4 (32 Meg x 4 x 8 banks)
256M4
– 128 Meg x 8 (16 Meg x 8 x 8 banks)
128M8
– 64 Meg x 16 (8 Meg x 16 x 8 banks)
64M16
FBGA package (Pb-free) – x16
– 84-ball FBGA (8mm x 12.5mm) Rev. G
HR
FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (8mm x 11.5mm) Rev. G
HQ
Timing – cycle time
– 2.5ns @ CL = 5 (DDR2-800)
-25E
– 2.5ns @ CL = 6 (DDR2-800)
-25
– 3.0ns @ CL = 4 (DDR2-667)
-3E
– 3.0ns @ CL = 5 (DDR2-667)
-3
– 3.75ns @ CL = 4 (DDR2-533)
-37E
Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
None
– Industrial (–40°C ≤ TC ≤ 95°C;
–40°C
≤ TA ≤ 85°C)
IT
– Automotive (–40°C ≤ TC , TA ≤ 105C)
AT
Revision
:G
Note: 1. Not all options listed can be combined to
define an offered product. Use the Part
product offerings and availability.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
tRC (ns)
CL = 3
CL = 4
CL = 5
CL = 6
CL = 7
-25E
400
533
800
n/a
55
-25
400
533
667
800
n/a
55
-3E
400
667
n/a
54
-3
400
533
667
n/a
55
-37E
400
533
n/a
55
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Features
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.