參數(shù)資料
型號: MT46V128M4P-75L:C
元件分類: DRAM
英文描述: 128M X 4 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
文件頁數(shù): 8/94頁
文件大?。?/td> 4179K
09005aef80a1d9e7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MBDDRx4x8x16_2.fm - Rev. J 1/06 EN
16
2000–2005 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR SDRAM
Register Definition
Figure 7:
Mode Register Definition
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3 (DDR400 Only)
Reserved
2.5
Reserved
Burst Length
CAS Latency BT
0
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register
(Mx)
Address Bus
9
7
65
4
3
8
2
1
0
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
Operating Mode
A10
A12 A11
BA0
BA1
10
11
12
13
0
14
Operating Mode
Normal operation
Normal operation/Reset DLL
All other states reserved
0
1
-
0
-
0
-
0
-
0
-
0
-
Valid
-
M6-M0
M8 M7
M9
M10
M12 M11
Burst Length
Reserved
2
4
8
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
1
0
1
M2
0
1
0
1
0
1
Mode Register Definition
Base Mode Register
Extended Mode Register
Reserved
M14
0
0
1
M13
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