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參數(shù)資料
| 型號(hào)： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 12/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_1.fm - Rev. K 9/04 EN
2
2003 Micron Technology, Inc. All rights reserved.
Figure 2: 256Mb DDR SDRAM Part
Numbers
FBGA Part Marking System
Due to space limitations, FBGA-packaged compo-
nents have an abbreviated part marking that is differ-
ent from the part number. For a quick convertion of an
FBGA code, see the FBGA Part Marking Decoder on the
Micron web site, www.micron.com/decoder.
General Description
The 256Mb DDR SDRAM is a high-speed CMOS,
dynamic
random-access
memory
containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM.
The 256Mb DDR SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 256Mb DDR
SDRAM effectively consists of a single 2n-bit wide,
one-clock-cycle data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-
clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower
byte and one for the upper byte.
The 256Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby effectively providing
high bandwidth by hiding row precharge and activa-
tion time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive option outputs are SSTL_2, Class II compatible.
NOTE: 1. The functionality and the timing specifica-
tions discussed in this data sheet are for the
DLL-enabled mode of operation.
2. Throughout the data sheet, the various fig-
ures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ
collectively, unless specifically stated other-
wise. Additionally, the x16 is divided into
two bytes, the lower byte and upper byte.
For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS. For
the upper byte (DQ8 through DQ15) DM
refers to UDM and DQS refers to UDQS.
3. Complete
functionality
is
described
throughout the document and any page or
diagram may have been simplified to con-
vey a topic and may not be inclusive of all
requirements.
4. Any specific requirement takes precedence
over a general statement.
-
L
Special Options
Standard
Low Power
Configuration
MT46V
Package
Speed
Special
Options
Temperature
Configuration
64 Meg x 4
32 Meg x 8
16 Meg x 16
64M4
32M8
16M16
Package
400-mil TSOP
400-mil TSOP (lead-free)
8x14 FBGA
8x14 FBGA (lead-free)
TG
P
FG
BG
Speed Grade
tCK = 5ns, CL = 3
tCK = 6ns, CL = 2.5
tCK = 7.5ns, CL = 2
tCK = 7.5ns, CL = 2.5
-5B
-6
-6T
-75E
-75Z
-75
IT
Operating Temp
Standard
Industrial Temp
Example Part Number: MT46V16M16TG-75E
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| MT48H8M16LFB4-8IT:JTR | 8M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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