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參數(shù)資料
| 型號： | MT46V64M4FG-75Z |
| 元件分類： | DRAM |
| 英文描述： | 64M X 4 DDR DRAM, 0.75 ns, PBGA60 |
| 封裝： | 8 X 14 MM, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 8/83頁 |
| 文件大?。?/td> | 2343K |
| 代理商： | MT46V64M4FG-75Z |
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256Mb: x4, x8, x16
DDR SDRAM
09005aef8076894f
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256MBDDRx4x8x16_2.fm - Rev. K 9/04 EN
16
2003 Micron Technology, Inc. All rights reserved.
Commands
Table 5 and Table 6 provide a quick reference of
available commands, followed by a description of each
command. Two additional truth tables, Table 8 on
page 42, and Table 9 on page 44, appear following the
Operation section, provide current state/next state
information.
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0
–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0
–BA1 are reserved). A0-A12 provide the op-
code to be written to the selected mode register.
3. BA0
–BA1 provide bank address and A0–A12 provide row address.
4. BA0
–BA1 provide bank address; A0–Ai provide column address, (where i = 8 for x16, i = 9 for x8, and i = 9,11 for x4) A10
HIGH enables the auto precharge feature (non persistent); and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0
–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0
–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; within the self refresh mode, all inputs and I/Os are “Don’t Care”
except for CKE.
8. Applies only to READ bursts with auto precharge disabled; this command is undefined (and should not be used) for
READ bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
NOTE:
1. Used to mask write data; provided coincident with the corresponding data.
Table 5:
Truth Table – Commands
Note 1 applies to all commands.
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
NOTES
DESELECT (NOP)
HX
X
9
NO OPERATION (NOP)
LH
H
X
9
ACTIVE (Select bank and activate row)
L
H
Bank/Row
3
READ (Select bank and column, and start READ burst)
L
H
L
H
Bank/Col
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
Bank/Col
4
BURST TERMINATE
LH
HL
X
8
PRECHARGE (Deactivate row in bank or banks)
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LL
L
H
X
6, 7
LOAD MODE REGISTER
LL
Op-Code
2
Table 6:
Truth Table – DM Operation
Note 1 applies to all commands
NAME (FUNCTION)
DM
DQ
Write Enable
L
Valid
Write Inhibit
HX
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M4FJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-6T | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M4FJ-75Z | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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