參數(shù)資料
型號: MT47H64M16HR-3IT
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
文件頁數(shù): 10/129頁
文件大小: 9252K
代理商: MT47H64M16HR-3IT
Figure 64: Bank Write – with Auto Precharge
CK
CK#
CKE
A10
Bank select
tCK
tCH tCL
RA
tRCD
tRAS
tRP
WR4
T0
T1
T2
T3
T4
T5
T5n
T6
T7
T8
T6n
NOP1
Command
3
ACT
RA
Col n
WRITE2
NOP1
Bank x
NOP1
Bank x
NOP1
tDQSL tDQSH tWPST
DQ6
DM
WL ±tDQSS (NOM)
Don’t Care
Transitioning Data
tWPRE
DQS, DQS#
Address
T9
NOP1
WL = 2
DI
n
5
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing tWR (in ns) by tCK and
rounding up to the next integer value.
5. Subsequent rising DQS signals must align to the clock within tDQSS.
6. DI n = data-in from column n; subsequent elements are applied in the programmed order.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
WRITE
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
107
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H64M16HR-3L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM