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| 型號(hào)： | MT47H64M16HR-3IT |
| 元件分類： | DRAM |
| 英文描述： | 64M X 16 DDR DRAM, 0.4 ns, PBGA84 |
| 封裝： | 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84 |
| 文件頁(yè)數(shù)： | 18/129頁(yè) |
| 文件大?。?/td> | 9252K |
| 代理商： | MT47H64M16HR-3IT |
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Figure 69: Power-Down
CK
CK#
Command
NOP
Address
CKE
DQ
DM
DQS, DQS#
Valid
tCH
tCL
Enter
power-down
mode6
Exit
power-down
mode
Don’t Care
tCKE (MIN)2
Valid
Valid1
Valid
tXP3, tXARD4
tXARDS5
Valid
tIS
tIH
T1
T2
T3
T4
T5
T6
T7
T8
tCK
Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVATE
(or if at least one row is already active), then the power-down mode shown is active power-
down.
2. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2 × tCK + tIH. CKE must not transition
during its tIS and tIH window.
3. tXP timing is used for exit precharge power-down and active power-down to any non-
READ command.
4. tXARD timing is used for exit active power-down to READ command if fast exit is selec-
ted via MR (bit 12 = 0).
5. tXARDS timing is used for exit active power-down to READ command if slow exit is selec-
ted via MR (bit 12 = 1).
6. No column accesses are allowed to be in progress at the time power-down is entered. If
the DLL was not in a locked state when CKE went LOW, the DLL must be reset after
exiting power-down mode for proper READ operation.
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Power-Down Mode
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
114
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H64M16HR-3L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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