參數(shù)資料
型號: MT47H64M16HR-3IT
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.4 ns, PBGA84
封裝: 8 X 12.50 MM, ROHS COMPLIANT, FBGA-84
文件頁數(shù): 13/129頁
文件大?。?/td> 9252K
代理商: MT47H64M16HR-3IT
Functional Block Diagrams
The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory. It is inter-
nally configured as a multibank DRAM.
Figure 3: 256 Meg x 4 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
14
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode
registers
11
A0–A13,
BA0–BA2
14
Address
register
17
512
(x16)
8,192
Column
decoder
Bank 0
Memory array
(16,384 x 512 x 16)
Bank 0
row-
address
latch
and
decoder
16,384
Sense amplifiers
Bank
control
logic
17
Bank 1
Bank 2
Bank 3
14
9
3
2
Refresh
counter
4
2
RCVRS
16
CK out
DATA
DQS, DQS#
CK, CK#
COL0, COL1
CK in
DRVRS
DLL
MUX
DQS
generator
4
2
Read
latch
WRITE
FIFO
and
drivers
Data
4
16
1
Mask
1
4
2
Bank 1
Bank 2
Bank 3
Input
registers
DM
DQ0–DQ3
RAS#
CAS#
CK
CS#
WE#
CK#
Command
decode
CKE
ODT
I/O gating
DM mask logic
DQS, DQS#
Vdd Q
R1
R2
sw1 sw2
Vss Q
sw1 sw2
ODT control
sw3
R3
sw3
R1
R2
sw1 sw2
R3
sw3
R1
R2
sw1 sw2
R3
sw3
1Gb: x4, x8, x16 1.55V DDR2 SDRAM
Functional Block Diagrams
PDF: 09005aef82b91d01
1GbDDR2_1_55V.PDF Rev. A 5/09 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H64M16HR-3L 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM