參數(shù)資料
型號(hào)： MT55L512V18PF-6
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 512K X 18 ZBT SRAM, 3.5 ns, PBGA165
封裝： 13 X 15 MM, FBGA-165
文件頁(yè)數(shù)： 12/25頁(yè)
文件大?。?/td> 304K
代理商： MT55L512V18PF-6
2
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
36
K
MODE
18
BWa#
BWb#
BWc#
BWd#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
DQs
DQPa
DQPb
DQPc
DQPd
D
A
T
A
S
T
E
R
I
N
G
O
U
T
P
U
T
B
U
F
E
R
S
256K x 8 x 4
(x32)
256K x 9 x 4
(x36)
MEMORY
ARRAY
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
16
18
BURST
LOGIC
SA0'
SA1'
D1
D0
Q1
Q0
SA0
SA1
K
18
ADV/LD#
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CKE#
WRITE
DRIVERS
SA0, SA1, SA
36
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams
for detailed information.
FUNCTIONAL BLOCK DIAGRAM
256K x 32/36
FUNCTIONAL BLOCK DIAGRAM
512K x 18
18
SA0, SA1, SA
K
MODE
19
BWa#
BWb#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
DQs
D
A
T
A
S
T
E
R
I
N
G
O
U
T
P
U
T
B
U
F
E
R
S
512K x 9 x 2
MEMORY
ARRAY
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
19
17
19
BURST
LOGIC
SA0'
SA1'
D1
D0
Q1
Q0
SA0
SA1
K
19
ADV/LD#
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CKE#
WRITE
DRIVERS
18
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