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參數(shù)資料
| 型號： | MT55L512V18PF-6 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 18 ZBT SRAM, 3.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, FBGA-165 |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 304K |
| 代理商： | MT55L512V18PF-6 |
16
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L512L18P_C.p65 – Rev. 2/02
2002, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
PIPELINED ZBT SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C
≤ T
A ≤ +70°C; VDD = +3.3V ±0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
VIHQ
1.7
VDDQ + 0.3
V
1, 2
Inputs
VIH
1.7
VDD + 0.3
V
1, 2
Input Low (Logic 0) Voltage
VIL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
≤ VIN ≤ VDD
ILI
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
ILO
-1.0
1.0
A
0V
≤ VIN ≤ VDDQ (DQx)
Output High Voltage
IOH = -2.0mA
VOH
1.7
–
V1
IOH = -1.0mA
VOH
2.0
–
V1
Output Low Voltage
IOL = 2.0mA
VOL
–
0.7
V
1
IOL = 1.0mA
VOL
–
0.4
V
1
Supply Voltage
VDD
3.135
3.465
V
1
Isolated Output Buffer Supply
VDDQ
2.375
2.9
V
1
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH
≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot:
VIL
≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up:
VIH
≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10A.
4. This parameter is sampled.
5. Preliminary package data.
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A = +25°C; f = 1 MHz
CI
34
pF
4
Input/Output Capacitance (DQ)
VDD = +3.3V
CO
45
pF
4
Address Capacitance
CA
3
3.5
pF
4
Clock Capacitance
CCK
3
3.5
pF
4
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Address/Control Input Capacitance
CI
2.5
3.5
p F
4, 5
Output Capacitance (Q)
T
A = 25°C; f = 1 MHz
CO
4
5
p F
4, 5
Clock Capacitance
CCK
2.5
3.5
p F
4, 5
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