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參數(shù)資料
| 型號： | MT57W4MH9CF-6 |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 DDR SRAM, 0.5 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 344K |
| 代理商： | MT57W4MH9CF-6 |
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4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
10
2003 Micron Technology, Inc.
Table 6:
Ball Descriptions
SYMBOL
TYPE
DESCRIPTION
BW_#
NW_#
Input
Synchronous Byte Writes (or Nibble Writes on x8): When LOW, these inputs cause their respective
byte to be registered and written if W# had initiated a WRITE cycle. These signals must meet setup
and hold times around the rising edges of K and K# for each of the two rising edges comprising the
WRITE cycle. See Ball Layout figures for signal to data relationships.
C
C#
Input
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C# is used as the output timing reference for the first output data. The rising edge of
C is used as the output reference for the second data. Ideally, C# is 180 degrees out of phase with C.
C and C# may be tied HIGH to force the use of K and K# as the output reference clocks instead of
having to provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during
device operation.
D_
Input
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K
and K# during WRITE operations. See Ball Layout figures for ball site location of individual signals.
The x8 device uses D0:D7. Remaining signals are NC. The x9 uses D0:D8. Remaining signals are NC.
The x18 device uses D0:D17. Remaining signals are NC. The x36 device uses D0:D35. Remaining
signals are NC.
DLL#
Input
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency
operation.
K
K#
Input
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
LD#
Input
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of two data
(one clock period of bus activity).
R/W#
Input
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when
R/W# is HIGH; WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and
hold times around the rising edge of K.
SA
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions
operate on a burst of two words (one clock period of bus activity). These inputs are ignored when
both ports are deselected.
TCK
Input
IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to VSS if the JTAG function is not used
in the circuit.
TMS
TDI
Input
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left as No Connects if the JTAG function is
not used in the circuit.
VREF
Input
HSTL Input Reference Voltage: Nominally VDDQ/2, but may be adjusted to improve system noise
margin. Provides a reference voltage for the HSTL input buffer trip point.
ZQ
Input
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to
ground. Alternately, this ball can be connected directly to VDDQ, which enables the minimum
impedance mode. This ball cannot be connected directly to GND or left unconnected.
CQ#, CQ
Output
Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run freely and do
not stop when Q tri-states.
TDO
Output
IEEE 1149.1 Test Output: 1.8V I/O level.
Q_
Output
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K#
rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball
Layout figures for ball site location of individual signals. The x8 device uses Q0:Q7. Remaining
signals are NC. The x9 uses Q0:Q8. Remaining signals are NC. The x18 device uses Q0:Q17. Remaining
signals are NC. The x36 device uses Q0:Q35. Remaining signals are NC.
VDD
Supply
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range.
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| MT57W512H36BF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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| MT57W512H36JF-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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