參數(shù)資料
型號： MT57W4MH9CF-6
元件分類： SRAM
英文描述： 4M X 9 DDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FBGA-165
文件頁數(shù)： 7/29頁
文件大小： 344K
代理商： MT57W4MH9CF-6
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V VDD, HSTL, DDR SIO SRAM
ADVANCE
36Mb: 1.8V VDD, HSTL, QDRB2 SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT57W2MH18C_B.fm – Rev. B, Pub. 2/03
15
2003 Micron Technology, Inc.
Table 11:
IDD Operating Conditions and Maximum Limits
Notes appear following parameter tables on page 17; 0°C
TA +70°C; VDD = 1.8V ±1.0V unless otherwise noted
MAX
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-3
-3.3
-4
-5
-6
-7.5
UNITS
NOTES
Operating Supply
Current: DDR
Cycle time
tKHKH
(MIN
); Outputs open;
x:1 ratio for READs to
WRITEs; 50% address
and data bits
toggling on each
clock cycle
IDD
x8, x9, x18
x36
TBD
525
710
475
640
400
545
330
445
280
380
235
310
mA
Standby Supply
Current: NOP
tKHKH = tKHKH
(MIN);
Device in NOP state;
All addresses/data
static
ISB1
x8, x9, x18
(x36)
TBD
255
265
235
240
200
210
170
180
150
160
125
135
mA
Output Supply
Current: DDR
(Information only)
CL = 15pF
IDDQ
x8, x9
x18
x36
TBD
42
95
189
38
85
170
32
71
142
25
57
113
21
47
95
17
38
76
mA
Table 12:
Capacitance
Note 13; notes appear following parameter tables on page 18
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
Address/Control Input Capacitance
TA = 25°C; f = 1 MHz
CI
4.5
5.5
pF
Input, Output Capacitance (D, Q)
CO
67
pF
Clock Capacitance
CCK
5.5
6.5
pF
Table 13:
Thermal Resistance
Note 13; notes appear following parameter tables on page 18
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS
NOTES
Junction to Ambient (Airflow of 1m/s)
Soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
qJA
19.4
°C/W
Junction to Case (Top)
qJC
1.0
°C/W
Junction to Balls (Bottom)
qJB
9.6
°C/W
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