參數(shù)資料
型號： MT5TL8L32T-50IT
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝： TQFP-100
文件頁數(shù)： 26/31頁
文件大小： 584K
代理商： MT5TL8L32T-50IT
MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
4
ADVANCE
Melody Routing Coprocessor
DQ31–0 (DATA BUS, THREE-STATE, COMMON
INPUT/OUTPUT)
The DQ31–0 lines convey data to and from the
Melody RCP. When the E# input is HIGH the DQ31–0
lines are held in their high-impedance state. The W#
input determines whether data flows to or from the
device on the DQ31–0 lines. The source or destination
of the data is determined by the AC bus, DSC, and the
AV# line. During a Write cycle, data on the DQ31–0 lines
is registered by the falling edge of E#.
AC12–0/AC11–0 (ADDRESS/CONTROL BUS, INPUT)
When Hardware control is selected, the AC bus
conveys address or control information to the Melody
RCP, depending on the state of the AV# input. When AV#
is LOW then the AC bus carries an address; when AV# is
HIGH the AC bus carries control information. Data on
the AC bus is registered by the falling edge of E#. When
software control is selected, the state of the AC bus does
not affect the operation of the device.
DSC (DATA SEGMENT CONTROL, INPUT)
When DQ bus access to a 64 bit register or memory
word is performed, the DSC input determines whether
bits 31–0 (DSC LOW) or bits 63–32 (DSC HIGH) are
accessed. Access to 32 bit registers require that DSC be
held LOW.
AA12–0/AA11–0 (ACTIVE ADDRESS, OUTPUT)
The AA bus conveys the Match address, the Next Free
address, or Random Access address, depending on the
most recent memory cycle. The OE# input enables the
AA bus; when the OE# input is HIGH, the AA bus is in its
high-impedance state; when OE# is LOW the AA bus is
active. In a vertically cascaded system after a Compar-
ison cycle, Write at Next Free Address cycle or Read/
Write at Highest-Priority match, only the highest-
priority device enables its AA bus, regardless of the state
of the OE# input. In the event of a mismatch in the
Address Database after a Compare cycle, or after a Write
at Next Free Address cycle into an already full system,
the lowest-priority device drives the AA bus with all 1s.
The AA bus is latched when E# is LOW, and are free to
change only when E# is HIGH. Melody RCP Pinout
PA3–0 (PAGE ADDRESS, OUTPUT)
The PA3–0 lines convey Page Address information.
When the OE# input is HIGH, the PA3–0 outputs are in
their high-impedance state; when OE# is LOW the PA3–
0 lines carry the Page Address value held in the Configu-
ration register. The PA3–0 lines are latched when E# is
LOW, and are free to change only when E# is HIGH. The
Page Address value of the currently active or highest-
priority responding device is output at the same time,
and under the same conditions, as the AA bus is active.
E# (CHIP ENABLE, INPUT)
The E# input is the main chip enable and synchro-
nizing control for the Melody RCP. When E# is HIGH,
the chip is disabled and the DQ31–0 lines are held in
their high-impedance state. The falling edge of E#
registers the W#, CS#1, CS#2, AV#, AC# bus, DSC, and
the VB# and DQ31–0 lines for a Write cycle. E# being
LOW causes the results of the previous comparison or
memory access to be latched on the PA:AA bus; when
E# goes HIGH the latches opens allowing the new
comparison results or random access memory address
to flow to the PA:AA bus.
CS#1, CS#2 (CHIP SELECT 1, CHIP SELECT 2,
INPUTS)
The CS#1 and CS#2 inputs enable the Melody RCP. If
either CS#1 or CS#2 are LOW, the device is selected for a
Read, Write, or Compare cycle through the DQ31–0
lines, or for an internal data transfer. The CS#1 and
CS#2 lines do not have any effect on the PA:AA bus. The
state of the CS#1 and CS#2 lines is registered by the
falling edge of E#.
W# (WRITE ENABLE, INPUT)
The W# input determines the direction of data
transfer on the DQ31–0 lines during Read, Write, and
Data Move cycles. When W# is LOW, data flows into the
DQ31–0 lines; when W# is HIGH, data flows out. The W#
line also conditions the control state present on the AC
bus and DSC lines. The state of the W# line is registered
by the falling edge of E#.
OE# (OUTPUT ENABLE, INPUT)
The OE# input enables the PA:AA bus. When OE# is
HIGH, PA:AA bus are in their high-impedance state.
When OE# is LOW, PA:AA bus are active, and convey the
results of the last Comparison Cycle Match address or
Memory Access address. In a vertically cascaded
system, only the PA:AA bus of the highest-priority
device is activated by OE# being LOW; in lower-priority
devices, the PA:AA bus remains in high-impedance
regardless of the state of OE#.
AV# (ADDRESS VALID, INPUT)
When Hardware control is selected, the AV# input
determines whether the AC bus carries address or
control information. When AV# is LOW, the AC bus
conveys a memory address; when AV# is HIGH, the AC
bus conveys control information. The state of the AV#
line is registered by the falling edge of E#. When
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