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參數(shù)資料
| 型號： | MT5TL8L32T-50IT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 584K |
| 代理商： | MT5TL8L32T-50IT |
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MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
6
ADVANCE
Melody Routing Coprocessor
TDO (JTAG TEST DATA OUTPUT, OUTPUT)
The TCLK output is the Test Data Output. This pin is
internally pulled up.
TRST# (JTAG RESET, INPUT)
The TRST# input is the Reset input, and serves to
reset the Test Access Port circuitry to its reset condition.
This pin is internally pulled up.
VDD, VSS (POSITIVE POWER SUPPLY, GROUND)
These pins are the main power supply connections to
the Melody RCP. VDD must be held at +3.3V and ±0.3V
relative to the VSS pin, which is at 0V, system reference
potential, for correct operation of the device.
Note:
The TCLK, TMS, TDI, TDO, and TRST# lines
are defined in the IEEE Standard Test Access
Port and Boundary-scan Architecture IEEE
Standard. 1149.1-1990 and IEEE Standard.
1149.1a-1993.
FUNCTIONAL DESCRIPTION
Data is read from and written to the Melody RCP
through the DQ31–0 lines. The Control bus, which is
comprised of Chip Enable (E#), two Chip Selects (CS#1,
CS#2), Write Enable (W#), Output Enable (OE#), Validity
Bit Control (VB#), Address Valid (AV#), Data Segment
Control (DSC), and the Address/Control inputs (AC bus)
controls the Melody RCP. When the AV# line is LOW, the
AC bus carries an address for random access into the
Memory array; when it is HIGH, the AC bus conveys
control information. The Melody RCP control states
perform Register Read/Write, Memory Read/Write,
Data Move, Comparison, Validity Bit Control, Initializa-
tion, and Address Register Control. These functions are
summarized in See
Random access to memory locations occurs when
the AV# line is LOW; during a Write cycle, the validity of
the location is set by the VB# input. When the AV# line is
HIGH the control states allow read and write access to
the register set comprising Comparand register, seven
mask registers, a Configuration register, a Status
register, an Address register, a Device Select register, and
an Instruction register. The Configuration register sets
the persistent operating conditions of the device: the
Page address of the device, selection of mask register for
directly addressed memory writes, and selection
between hardware and software control.
When Hardware control is selected, control is
through the AC bus and DSC line. When Software
control is selected, control is through the Instruction
register, which is loaded from the DQ bus. Under
software control the AV# line is used to distinguish
between data and an instruction on the DQ bus. There-
fore, in Software Control mode, random access to the
Memory array can take place only using indirect
addressing through the Address register.
The two Chip Select lines CS#1, CS#2 enable the
device and simplify access to a multi-chip system, if
either Chip Select line is LOW the device is selected. The
Melody RCP also can be selected through the Device
Select register when its value is set to that of the Page
address of the device, and the enable bit in the Device
Select register is set LOW. The OE# input enables the
output signal and is used to synchronize devices in a
multi-chip system, and to prevent race conditions
among devices during priority resolution.
The output signals comprise the Active address (AA
bus), and the Page address (PA bus). The PA:AA bus
provides the current Active address, which is either the
Match address, Next Free address, or the Random
Access address, concatenated with the Device Page
address. The source of Active address is dependent on
the previous control state, allowing access to associated
data in the external RAM at the same location as an
access in the Melody RCP for all types of cycles.
The Output enable, OE#, controls the PA:AA bus:
when it is LOW after a Compare cycle, the highest-
priority responding device outputs its Page and Match
addresses on PA:AA bus. Only the highest-priority
responding device is enabled, all other lower-priority
devices will have their PA:AA bus in the high-imped-
ance state, regardless of the state of their respective OE#
lines: when OE# is HIGH, the PA:AA remain in the high-
impedance state.
When a mismatch occurs in the system, the lowest-
priority device, as defined in the Configuration
register, drives the PA:AA bus with all 1s. When any
Read or Write cycle occurs, the address of the accessed
location is output on the PA:AA bus. The address
output on the PA:AA bus is persistent, and is held
latched until E# goes HIGH during the next cycle that
changes the Active address. The PA:AA bus is free to
change only while E# is HIGH. Once E# goes LOW, the
state of the PA:AA bus is latched.
After a Compare cycle, the MF# and MM# flags are
free to change after E# has gone HIGH. Once the Match
Flag daisy chain has resolved device prioritization, the
OE# lines can be asserted to enable the PA:AA bus from
the highest-priority matching device.
In a multi-chip system, when a device remains
deselected during a Compare cycle through CS#1 and
CS#2 being HIGH and there being no match between
the Device Select register and the Page Address register,
that device clears any previous positive match results.
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