參數(shù)資料
型號: MT5TL8L32T-50IT
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝: TQFP-100
文件頁數(shù): 4/31頁
文件大?。?/td> 584K
代理商: MT5TL8L32T-50IT
MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
12
ADVANCE
Melody Routing Coprocessor
The conditions of the Device Select register, the
CS#1 and CS#2 lines are sampled at the time of the
falling edge of E#. In a particular Melody RCP within a
system, that CAM will be selected under the following
conditions:
Therefore, the CS#1 lines of all devices are tied
together for global cycles that broadcast control states
to all devices within the system; then, for local cycles, an
individual device is selected by loading all the Device
Select Registers bit DS8 LOW and bits DS3–0 with the
Page Address value of the device to be selected. On a
subsequent cycle, CS#1 and CS#2 remain HIGH, and
only the device whose Page Address value matches with
its DS3–0 responds. After an individual device has been
selected, a global Write cycle to the Device Select
register using CS#1 line is executed to select another
device, or to disable the software chip select mecha-
nism altogether.
VERTICAL CASCADING
A system of any practical depth can be designed by
vertically cascading Melody RCPs. The scheme uses a
daisy chain to provide system level prioritization as well
as Match, Multiple Match, and Full flags. There are three
daisy chains: Match, Multiple Match, and Full.
When a control state is broadcast that accesses the
highest-priority matching location or Status register,
the daisy chain ensures that only the device that
responds is the one with the highest-priority match in
the system. All other devices will have their DQ31–0
lines and PA:AA bus outputs held in high-impedance.
Therefore, the Match Flag daisy chain controls access to
the system resources for control states that are condi-
tional on the results of the previous Compare cycle.
During a Comparison cycle, the Match and Multiple
Match flags do not change until E# goes HIGH during
that cycle. At this time, the daisy chain starts to resolve
system-level prioritization. Once sufficient time has
elapsed for the daisy chain to be resolved, the PA:AA bus
can be enabled with OE#, and Status Register Read
cycles access only the highest-priority matching device.
Note that the daisy chain resolves system-level prioriti-
zation combinatorially once initiated by E# going HIGH.
Other cycles that do not affect the daisy chain or match
results can take place in the Melody RCP while the daisy
chain is resolving, for example, WR CR, allowing some
degree of pipelining. During a Write cycle, the Full flag
does not change until E# goes HIGH during that cycle.
There is a small propagation delay per device in the
daisy chain. Alternatively, vertical cascading can be
done with external logic that provides prioritization and
select lines back into each device. The Melody RCP
architecture supports external prioritization for cases
where the daisy chain overhead proves unacceptable.
Figure 3 on page 12 shows a system in which a number
of Melody RCPs are vertically cascaded.
Figure 3. Vertically Cascading Melody RCPs
Full Cascading
The Full flag is set LOW in a particular Melody RCP if
the FI# line is LOW, and that device is full. During a
Write cycle, the Full flag does not change until E# goes
HIGH during that cycle. When the FI# line is HIGH, one
or more locations are free in the higher-priority devices;
therefore, when the FI# line is HIGH, whether or not
that particular device is full, its FF# output remains
HIGH. This method allows the Full Flag daisy chain to
recognize non-contiguous empty locations throughout
the entire Melody RCP system.
The daisy chain gives System Full indication. When
the device at the end of the chain has its FF# output
LOW, the entire CAM system is full. The first device in
(CS#1 = LOW) OR (CS#2 = LOW)
OR ((DS8 = LOW) AND (DS3–0 = PA3–0))
Melody
+3.3V
’0’
’1’
MII#
FII#
MFI#
FFI#
MMI#
MII#
FII#
MFI#
FFI#
MMI#
MII#
FII#
MFI#
FFI#
MMI#
Match
Full
Multiple-match
Lowest Priority
Highest Priority
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