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參數(shù)資料
| 型號(hào)： | MT5TL8L32T-50IT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 584K |
| 代理商： | MT5TL8L32T-50IT |
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MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
14
ADVANCE
Melody Routing Coprocessor
INITIALIZATION
After power is applied to the Melody RCP the RESET#
line must be pulled LOW for at least 50ns to ensure that
the device establishes its correct initial operating condi-
tions. There are control states to initialize the system-
level operating conditions that can be run once the
device or devices in the system have been reset after
power has been applied.
Reset
The Reset condition occurs when the RESET# line is
pulled LOW (Hardware reset,) or when the Reset
Control state is executed (Software reset.) The condi-
tions after a reset are shown in Table 3.
The Instruction register is enabled for Software
Control mode. To activate Hardware control, the appro-
priate value should be written to the Configuration
register in two cycles from the DQ31–0 lines.
For a Hardware reset, FR25, which defines the lowest
priority device, is set HIGH. This means that either FR25
must be set LOW in the lowest-priority device, or a
Memory access cycle or a Compare cycle that generates
a match must be executed for there to be any response
when reading the PA:AA bus or the Status register.
System Initialization
Once the Melody RCP devices in the system have
been reset, the system operating conditions must be
set up. The Melody RCP is reset to Software Control
mode, so a value must be written to the Configuration
register to set the persistent operating state of the
device. This first write to the devices in the system
must be through Software control. The following
sequence writes a new value to the Configuration
register under software control:
1. Write 006H to Melody RCPs (AV# = HIGH, DQ13 =
LOW).
2. The value 006H is the control state Write to Con-
figuration register, WR FR, with no mask. AV#
being HIGH indicates that this is the instruction
to be written to the Instruction register, and DQ13
being LOW indicates that it is a Write cycle.
3. Write XXXXXXXXH to Melody RCPs (AV# = LOW).
4. The value XXXXXXXXH is written to the Configura-
tion register, and if FR27–26 = 00 then the devices
are set to operate in Hardware Control mode. AV#
being LOW causes the control state to execute
using the data present on the DQ31–0 lines.
If the devices in a vertically cascaded system are to be
selected solely through the Device Select register, then
the Page addresses must be set to unique values in each
device. However, to set the Page address in each Config-
uration register in turn would require that each device
already had a unique Page Address value. To overcome
this dilemma, there are two special control states that
allow the Page Address registers to be set individually in
this circumstance. Once the general operating condi-
tions have been established by broadcasting a configu-
ration value to all the Melody RCPs in the system, the
Page Address values must be set to a unique value in
each device. This is done through a sequence of WR PA
control states, each executed with a unique value on the
DQ31-0 lines. This control state writes the DS3–0 value
into the Page Address field of the Configuration register
of the highest-priority empty device, and then sets the
Full flag of that device to indicate full (LOW). The next
WR PA is therefore be directed to the next lower-priority
device within the system. The sequence continues until
all Page Address values have been written. The RST FF
control state is then broadcast to all devices to set the
Full flags back to Empty, and the system is then ready
for normal operation.
JTAG
For detailed information on JTAG testing, refer to
the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Std. 1149.1-1990 and 1149.1a-1993.
The Melody RCP Instruction register is 3 bits long,
giving eight possible JTAG instructions. The least
significant bit is clocked in first. The JTAG instructions
are as follows:
The MT75L4L32MLQ IDCode is: X4000133H The
MT75L8L32MLQ IDCode is: XAC08133H (X is the four-
bit revision code)
BSDL files are available; check the Micron Web site or
contact Micron Technical Support.
JTAG FUNCTION
INSTRUCTION
EXTEST
000
RESERVED
001
RESERVED
010
CLAMP
011
IDCODE
100
INTEST
101
SAMPLE/PRELOAD
110
BYPASS
111
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