參數(shù)資料
型號: MT5TL8L32T-50IT
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100
封裝: TQFP-100
文件頁數(shù): 29/31頁
文件大?。?/td> 584K
代理商: MT5TL8L32T-50IT
MUAC Routing Coprocessor
2002, Micron Technology Inc.
DS-MUAC RCP 8K and 4K.fm - Rev March/13/02/ 02:20 PM
7
ADVANCE
Melody Routing Coprocessor
In other words, if it had previously been indicating a
match from an earlier Comparison cycle, it is now set to
indicate a mismatch, even though it was not selected
during the most recent Compare cycle.
For pure software control of the Melody RCP, instruc-
tions can be loaded into the Instruction register, and
results read from the Status register. The Status register
holds the results of comparison: PA:AA bus, MF#, FF#,
and MM# plus two PA:AA Validation bits that indicate
the type of cycle that generated the PA:AA bus value.
Vertical cascading is supported through a daisy
chain architecture. There are two daisy chains, one
each for the Match flag and the Full flag; the Multiple
Match flag is connected between devices through an
open-drain line. The Match flag (MF#) from a higher-
priority device is connected to the Match input (MI#)
of the next lower-priority device to provide prioritiza-
tion throughout a multiple device system. The MF#
output from the lowest-priority device provides a
system Match flag. If the delay through the daisy chain
is unacceptable, the OE# input can be used by external
priority-resolution circuitry to enable the highest-
priority responder in the system.
The match conditions on the Match and Multiple
Match flag lines are persistent indicating the results of
the most recent Compare cycle. The Match flags are free
to change after the rising edge of E# during a Compare
cycle, at which time the daisy chain starts to resolve
device prioritization. Once the daisy chain has settled,
the OE# lines can be pulled LOW to access the Highest-
Priority Match address on the PA:AA bus.
The Multiple Match open-drain output (MM#)
provides multiple match indication when there are two
or more matches in a single device, or a device has its
MI# input LOW and has a match; the MM# flags of all
devices in the system are wire-ORed. Multiple
responders can be accessed sequentially by resetting
the Highest-Priority Match latch with the control state
Advance to Next Matching Location.
The Full flag (FF#) is cascaded from one device to the
Full Flag input (FI#) of the next lower-priority device in
the system. The FF# output from the lowest-priority
device provides a system Full flag. The Full flag is free to
change after the rising edge of E# during a Write cycle.
The daisy chains are persistent and are not conditioned
by the OE# input.
The Melody RCP supports JTAG boundary-scan
testing through the pins TCK, TMS, TDI, TDO, and
TRST#, according to the IEEE 1149 Standard: Test
Access Port and Boundary-scan Architecture.
OPERATIONAL CHARACTERISTICS
PROCESSOR INTERFACE
The processor interface is through a 32-bit data bus
DQ31–0 and control signals comprised of Chip Enable
(E#), two Chip Selects (CS#1, CS#2), Write Enable (W#),
Output Enable (OE#), Validity Bit Control (VB#),
Address Valid (AV#), Data Segment Control (DSC), and
Address/Control inputs (AC bus). When the AV# line is
LOW, the DSC and AC bus carries an address for
random access into the Memory array; when it is HIGH,
the AC bus conveys control information.
Most of the functionality of the Melody RCP is
accessed through the control states on DSC and AC bus
when AV# is HIGH. The processor maps the control
structure into memory space and controls the Melody
RCP through memory Read and Write cycles. Using this
memory mapping scheme, the AV# line should be
driven from logic that generates a HIGH level within the
mapped range of the control states, and a LOW level
outside it. Other control inputs E#, W#, CS#1, and CS#2
are analogous to SRAM control inputs.
The VB# line acts like an extra data bit during
memory Read and Write cycles and is used to read and
write the validity of any memory location.
The Melody RCP is enabled either through hardware
through CS#1 or CS#2 being LOW, or it is enabled by
the value written to the Device Select register
matching with the Page Address field of the Configura-
tion register. One extra bit in the Device Select register
enables the comparison between the Page Address
value and the Device Select register. These Chip Select
mechanisms operate in parallel. If any one is active,
the device is enabled.
The Melody RCP can be controlled directly through
software. The Software Control mode is selected
through settings in the Configuration register.
When the Software Control mode is selected, control
states are written to the Instruction register from DQ11–
0 during a Write cycle with the AV# line held HIGH.
DQ12 acts as the DSC input. If the control state does not
involve any data transaction on the DQ31–0 lines, the
instruction is executed during the same cycle; the state
of DQ13 modifies the instruction, its state is equivalent
to the W# input.
Note:
The system designer must ensure that the
correct cycle type follows the loading of an
instruction in Software Control mode. When
the instruction expects a Read cycle, and a
Write cycle is executed, or vice versa, the
function of the Melody RCP is undefined.
Such an error may lead to data loss, but does
not physically damage the device.
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