參數(shù)資料
型號(hào)： MT90503
廠商： Zarlink Semiconductor Inc.
英文描述： 2048VC AAL1 SAR
中文描述： 2048VC AAL1特區(qū)
文件頁(yè)數(shù)： 85/233頁(yè)
文件大?。?/td> 1341K
代理商： MT90503
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MT90503
Data Sheet
85
Zarlink Semiconductor Inc.
Finally, this value is used as the byte-pointer to the LUT entry, offset from the LUT base address for that port.
Figure 40 - VPI/VCI Concatenation and LUT Entry Address Example
4.5.6.3 UTOPIA Clocks
Each of the three ports must have a clock to operate the receive interface and a clock to operate the transmit
interface. Two or more clocks may have the same source. These clocks can either be input to the MT90503 from an
external source or output from the MT90503, from one of three internal UTOPIA clocks. For each port the transmit
clock and receive clock must be configured to be either both input or both output. An exception is Port C where
both transmit clock and receive clock must be input only.
The source of the each of the three internal UTOPIA clocks can be one of eight clocks: mclk, fast_clk, or any of the
six UTOPIA clocks (rxa, rxb, rxc, txa, txb, and txc). The selected clock is divided by n, an integer from 1 to 16, and
can be inverted.
Other parts of the UTOPIA module, including the look-up engine, the TX_SAR portion and the RX_SAR portion
operate off of mclk.
4.5.7 LED Operation
The UTOPIA module generates two LED signals for Port A (pins D2, H5) and two LED signals for Port B (pins W5,
T5) in order to indicate the status of the A and B ports. The status conditions are: idle, presence of traffic, or PHY
alarm. When a port is in an idle state, both its LEDs are illuminated. If RX traffic (other than null cells) is flowing,
then the RX LED for that port will flash; If TX traffic (other than null cells) is flowing, then the TX LED for that port will
flash. If a PHY alarm is detected, the TX LED is on and the RX LED is off. The polarity of the LED signals is
active-low, i.e., a ‘0’ will turn the LED on. The frequency of the LEDs is programmed in registers 0120h and 0122h
while the LEDs are enabled in register 0302h.
0 0 0 0
LUT Base Address (reg. 0320h)
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Notes:
This example is for port A and for
short LUT entries. All three ports
have independent parameters
(vci_n, num_vpi_vci_bits, LUT Base
Address).
Identifier is a pointer, offset from the
LUT Base Address, to the first byte
of the LUT entry.
Identifier is appended with either
"00" (short LUT entries) or "000"
(long LUT entries).
LUT Base Address comprises bits
19:4 of the base address. "0000" is
appended.
LUT Entry Address represents a
byte address
LUT Entry Address
VCI
VPI
vci_na (reg. 0324h) = 5 VCI Bits
Concatenated VPI and VCI
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
. . . . . . . . . . . . . . . . . . . . .
identifier
Σ
b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
b15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b0
0
0
num_vci_vpi_bits (reg. 322h) = 16
相關(guān)PDF資料
PDF描述
MT90503AG CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90503AG 制造商:Microsemi Corporation 功能描述:
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