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參數(shù)資料
| 型號： | MULTISYNCFE750 |
| 英文描述： | Monitor_ICs:HD6433577 LA7841 BA9761F MQ571 XC13289LSP LSC3820P2 uPD61882A |
| 中文描述： | Monitor_ICs：HD6433577 LA7841 BA9761F MQ571 XC13289LSP LSC3820P2 uPD61882A |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 517K |
| 代理商： | MULTISYNCFE750 |
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16
MON08 Multilink User Manual
P&E
Microcomputer
Systems, Inc.
MON08 MULTILINK
PORTA1, PORTB0, PORTB1 and PORTB4 are used for entering monitor
mode. By default the user may directly bring these signals out to the target
MON08 Header.
Alternatively, the user may pull up PORTB0, pull down PORTA1 and
PORTB1, and pull up/down PORTB4 for clock division. In which casethe user
does not need to connect these signals to the target MON08 Header.
3.10
68HC908GR4/8
Figure 3-10: 68HC908GR4/8 MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The target RESET line is directly connected to the Pin 4 of the target MON08
Header.
Alternatively, the user may pull up the RESET line to target VDD. In which
case the user does not need to connect this signal to the target MON08 Header.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 8, acting as the communications line. The MON08 MULTILINK pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTA1, PORTB0, and PORTB1 are used for entering monitor mode. By
default the user may directly bring these signals out to the target MON08
Header.
Alternatively, the user may pull up PORTB0, pull down PORTA1 and
PORTB1. In which case the user does not need to connect these signals to the
target MON08 Header. The clock division is fixed Div 4.
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