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參數(shù)資料
| 型號： | OM11079 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 32/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | MODULE DIMM LPC3250 ARM9 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 附件類型： | 模塊卡 |
| 適用于相關(guān)產(chǎn)品： | ARM-57TS-LPC3250 |
| 相關(guān)產(chǎn)品： | 622-1033-ND - KIT LCD TOUCH 5.7" FOR LPC2478 568-4743-ND - KIT LCD TOUCH 5.7" FOR LPC3250 568-4741-ND - KIT LCD TOUCH 5.7" FOR LPC2478 622-1030-ND - KIT LCD TOUCH 5.7" FOR LPC3250 622-1028-ND - KIT LCD TOUCH 5.7" FOR LPC2478 |
| 其它名稱： | 568-4744 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
38 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Only a single master and a single slave can communicate on the interface during a given
data transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master. The SPI implementation on the
LPC3220/30/40/50 does not support operation as a slave.
7.8.2.1
Features
Supports slaves compatible with SPI modes 0 to 3.
Half duplex synchronous transfers.
DMA support for data transmit and receive.
1-bit to 16-bit word length.
Choice of LSB or MSB first data transmission.
64 16-bit input or output FIFO.
Bit rates up to 52 Mbit/s.
Busy input function.
DMA time out interrupt to allow detection of end of reception when using DMA.
Timed interrupt to facilitate emptying the FIFO at the end of a transmission.
SPI clock and data pins may be used as general purpose pins if the SPI is not used.
Slave selects can be supported using GPO or GPIO pins
7.8.3 SSP serial I/O controller
The LPC3220/30/40/50 contains two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.8.3.1
Features
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
Maximum SPI bus data bit rate of 12 (Master mode) and 12 (Slave mode) of the input
clock rate
DMA transfers supported by GPDMA
7.8.4 I2C-bus serial I/O controller
There are two I2C-bus interfaces in the LPC32x0 family of controllers. These I2C blocks
can be configured as a master, multi-master or slave supporting up to 400 kHz. The I2C
blocks also support 7 or 10 bit addressing. Each has a four word FIFO for both transmit
and receive. An interrupt signal is available from each block.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OM11079,598 | 功能描述:開發(fā)板和工具包 - ARM NXP LPC3250 SODIMM for IRD2.0 RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| OM11080,598 | 制造商:NXP Semiconductors 功能描述:LPC1768 CORTEX-M3 3.2" 2X40 LCD DISPLAY KIT, ARM CORTEX-M3 M - Boxed Product (Development Kits) |
| OM11082,598 | 功能描述:開發(fā)板和工具包 - ARM NXP LPC3250 IRD2.0-5.7"LCD/Lnx RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| OM11083 | 制造商:NXP Semiconductors 功能描述:EVAL LPCXPRESSO BASEBOARD 制造商:NXP Semiconductors 功能描述:BASEBOARD, FOR LPCXPRESSO, LPC1XXX 制造商:NXP Semiconductors 功能描述:BASEBOARD, FOR LPCXPRESSO, LPC1XXX; Silicon Manufacturer:NXP; Features:BaseBoard for LPCXpresso/mbed Board with a viariety of interfaces and I/O devices; SVHC:No SVHC (19-Dec-2012) ;RoHS Compliant: Yes |
| OM11083,598 | 功能描述:開發(fā)板和工具包 - ARM Embedded Artist Base LPCXpresso mbed RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
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