參數(shù)資料
型號(hào)： OM13013,598
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 11/61頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO IAR LPC1227 JLINKLITE
標(biāo)準(zhǔn)包裝： 1
類型： MCU
適用于相關(guān)產(chǎn)品： LPC1227
所含物品： 板
其它名稱： 568-6885
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
19 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory
transfers.
Supports multiple DMA cycle types and multiple DMA transfer widths.
Performs all DMA transfers using the single AHB-Lite burst type.
7.8 CRC engine
The Cyclic Redundancy Check (CRC) engine with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.8.1 Features
Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
Programmable seed number setting.
Supports CPU programmed I/O or DMA back-to-back transfer.
Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation
– 16-bit write: 2-cycle operation (8-bit
2-cycle)
– 32-bit write: 4-cycle operation (8-bit
4-cycle)
7.9 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
7.9.1 Features
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
7.10 UARTs
The LPC122x contains two UARTs. UART0 supports full modem control and RS-485/9-bit
mode and allows both software address detection and automatic hardware address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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