參數(shù)資料
型號: OM13013,598
廠商: NXP Semiconductors
文件頁數(shù): 31/61頁
文件大?。?/td> 0K
描述: BOARD DEMO IAR LPC1227 JLINKLITE
標準包裝: 1
類型: MCU
適用于相關產(chǎn)品: LPC1227
所含物品:
其它名稱: 568-6885
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
37 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
Conditions: VDD(3V3) = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
(3) System oscillator enabled with external clock input; IRC and system PLL disabled.
Fig 10. Sleep mode: Typical supply current IDD versus supply voltage VDD(3V3) for
different system clock frequencies
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
Fig 11. Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD(3V3)
VDD(3V3) (V)
3.0
3.6
3.4
3.2
002aag188
2
3
1
4
5
IDD
(mA)
0
33 MHz
(2)
24 MHz
(2)
12 MHz
(1)
1 MHz
(3)
4 MHz
(3)
002aag190
20
40
30
50
IDD
(μA)
10
temperature (°C)
-40
85
35
10
60
-15
VDD(3V3) = 3.6 V
3.3 V
3.0 V
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