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參數資料
| 型號： | ORT42G5-1BM484I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數： | 34/119頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPSC TRANSCEIVER 4CH 484-BGA |
| 產品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標準包裝： | 60 |
| 系列： | * |
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Lattice Semiconductor
ORCA ORT42G5 and ORT82G5 Data Sheet
21
Bit alignment times fall into two categories: realignment when the input serial data stream experiences an abrupt
phase change (as may occur when protection switching is performed between two paths having different delays),
and alignment from a no-signal condition. Realignment is very quick, since the PLL’s VCO is already locked on fre-
quency and only needs to adapt to the new phase. This re-alignment has been observed to require no more than
one microsecond when REFCLK[A:B] = 156.25 MHz.
Alignment from a no-signal condition has two components. First, there is the re-acquisition to the data’s frequency
and phase. The time required for re-acquisition to the data’s frequency is minimized by logic that periodically
switches the PLL to lock to the REFCLK[A:B] when it fails to lock on the serial data stream, thus limiting the VCO’s
frequency wander. Second, there is the time spent while the PLL is locking to REFCLK[A:B], which can be from
zero to a maximum value, depending on when the serial data stream becomes valid in relation to the PLL’s switch-
ing to/from REFCLK[A:B]. This alignment has been observed to require no more than 4 microseconds when REF-
CLK = 156.25 MHz.
Byte alignment occurs once valid bit alignment is achieved. The byte aligner looks for a particular 7-bit sequence
(either 0011111 or its complement, 1100000) that, in data that has been 8b/10b encoded per Fibre Channel or
IEEE 802.3ae specications, only occurs in the comma (/K/) characters K28.1, K28.5 and K28.7. Byte alignment
only occurs when the ENBYSYNC_xx signal for that channel is active high, and re-alignment occurs on each 7-bit
sequence encountered. However, if ENBYSYNC_xx is asserted active high and no comma character is encoun-
tered, and then is brought inactive low, the channel will still perform one byte alignment operation on the next
comma character. Byte alignment occurs immediately when an alignment sequence is detected, so the lock time is
only one clock period.
Note: Each time the byte aligner performs an alignment, it also corrects the phase of the internal RBC_xx clock.
This can result in the “stretching” of the clock by a half-phase in order to cause the output data to align with the ris-
ing edge of RBC_xx.
Word (32-bit) alignment can occur after the Fibre Channel (XAUI_MODE_xx = 0) or XAUI (XAUI_MODE_xx = 1)
state machine has reached the in-synchronization state. In Fibre Channel mode, synchronization (WDSYNC_xx =
1) will occur after three ordered sets of data have been received in the absence of any code violations. After this,
the next ordered set will cause the output data to be aligned such that the comma character is in the most signi-
cant byte. Thus, 32-bit word alignment has been achieved when four ordered sets have been detected. The time
required is directly dependent on comma-character density.
Note: once word alignment is accomplished, no further alignment occurs unless and until WDSYNC_xx goes to
zero and back to one again. Comma characters that are not located in the most signicant byte position will not
trigger further re-alignment while WDSYNC_xx is active. This behavior is as dened by the Fibre Channel speci-
cation. However, it means that, if the channel experiences an abrupt delay change (as could occur if an external
MUX performs a protection switch between two links) and if the delay change is close enough to a full character or
characters that not enough code violations are generated to cause loss of WDSYNC_xx, the channel could
become misaligned and remain that way indenitely. As mentioned above, this behavior is that dened by the Fibre
Channel specication.
In XAUI mode, as the state diagram later in this data sheet indicates, three error-free code-groups containing com-
mas must be detected before synchronization is declared.
Multi 2, 4 or 8 (ORT82G5 only) channel alignment (Lane alignment in XAUI mode) can be performed after 32-
bit word alignment is complete. Multi-channel alignment is described in later sections of this data sheet.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| ORT42G5-1BMN484C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-1BMN484I | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BM484I | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT42G5-2BMN484C | 功能描述:FPGA - 現場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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